Technology mapping

Technology mapping is the step inside logic synthesis that translates an abstract, technology-independent network of Boolean operations into real gates drawn from a specific standard-cell library. Think of it as translating a recipe written in generic verbs ('combine,' 'reduce') into the exact appliances a particular kitchen owns — this oven, that blender, sized this way. The optimizer earlier found a good logical structure; mapping must now cover that structure with library cells (AND-OR-INV, complex AOI, full adders) so the result is fastest, smallest, or lowest-power for the chosen process.

The dominant technique covers the network with small patterns: decompose the logic into a base of 2-input gates or look-up tables, then run a dynamic-programming match that, working from inputs to outputs, picks the cheapest library cell covering each cone of logic. Modern tools (ABC's mapper) operate on And-Inverter Graphs and use 'cut enumeration' — listing the small sub-functions reachable at each node — to find low-depth, low-area covers. For FPGAs the same algorithm packs logic into k-input LUTs instead of cells.