Scan insertion
Scan insertion is the automated step where a DFT tool swaps every ordinary flip-flop in the netlist for its scan-equipped twin and then 'stitches' them all into chains. Think of it as walking through a finished building and replacing every regular door with a door that has a hidden service passage behind it, then connecting all those passages into one continuous corridor a maintenance crew can walk end to end.
The tool does more than wire flops in a line. It balances chain lengths so no chain is far longer than the others, orders the flops to keep the scan wiring short (a placement-aware decision), connects the scan-enable signal, and adds the dedicated scan input/output pins. It must also respect timing: the extra scan path and the scan-enable must not break the chip's functional speed. Done well, scan insertion is invisible in normal operation and only 'wakes up' when the scan-enable pin is asserted on the tester.
Scan insertion usually runs after logic synthesis and before place-and-route, so the physical tools can route the now-existing scan connections optimally.