property checking

Property checking is formal verification's flagship move: instead of running a finite number of test cases and hoping you covered the bad ones, a tool mathematically proves that a stated property holds for every possible input sequence the design could ever see — or hands you a concrete counterexample if it doesn't. Simulation is like tasting spoonfuls of soup to check for salt; property checking is like analysing the recipe to prove it can never be too salty, no matter what.

Under the hood the tool explores the design's entire state space symbolically (using SAT/BDD-based engines), so a proof is exhaustive in a way no amount of random testing can be. When it fails, the counterexample waveform it produces is gold: a minimal, reproducible recipe for the bug. The catch is the state-space explosion — large designs can be intractable, so engineers constrain inputs, decompose proofs, and target property checking at the hardest-to-simulate corners (arbiters, FIFOs, FSM deadlocks) where it earns its keep.