SystemVerilog assertion (SVA)

A SystemVerilog assertion is a tiny formal contract embedded directly in the design or testbench that says 'this must always be true' — and it watches, every clock, ready to scream the instant it isn't. For example: 'whenever req goes high, ack must follow within 1 to 4 cycles.' Written as a temporal property, the simulator checks it continuously and pinpoints the exact cycle of any violation. It's like a smoke detector wired into a specific room: silent until something goes wrong, then unmissable, and it tells you precisely where.

Assertions are powerful because they catch bugs at the moment and place of the violation, not three thousand cycles later when a corrupted result finally surfaces at an output — collapsing debug time dramatically. They also double as documentation of the design's true protocol intent, and the very same property can be both simulated dynamically and proven exhaustively by a formal tool. SVA's sequence/property syntax (|->, ##, throughout) is a compact temporal language for expressing 'this, then that, within this window.'