equivalence checking
Equivalence checking is the formal proof that two versions of a design compute exactly the same logic — typically the RTL a human wrote versus the gate-level netlist a synthesis tool produced, or a netlist before and after an automated optimization. Rather than simulating both and comparing outputs (which could only ever sample a tiny fraction of inputs), the tool mathematically proves the two are functionally identical for every input. It is like proving two algebraic expressions are equal by rearranging the symbols, instead of plugging in numbers and hoping.
This is what lets a design flow be trusted: synthesis, clock-tree insertion, scan stitching, and ECOs all transform the netlist, and after each step LEC re-proves nothing changed functionally — so a bug verified out at RTL can't sneak back in during physical implementation. The standard kind, combinational equivalence checking, relies on matching key points (registers and ports) between the two designs; when those points line up it is fast and exhaustive, which is why it runs routinely on multi-billion-gate chips where full re-simulation would be hopeless.
Equivalence checking proves the gates match the RTL — it cannot tell you the RTL was correct in the first place. That earlier question belongs to simulation, UVM, and property checking.