Computer architecture & accelerators

Network-on-chip (NoC)

Once a chip holds dozens of cores, caches, and accelerators, the old way of connecting them — a single shared bus everyone takes turns on — becomes a hopeless traffic jam. A network-on-chip replaces that bus with a miniature internet etched into the silicon: data travels in packets through a grid of routers, hopping from tile to tile, so many conversations happen at once on different paths instead of queuing for one wire.

Like a real network, a NoC has a topology (commonly a 2-D mesh of routers, one per tile), routing rules to steer packets, and flow control to avoid deadlock and congestion. The payoff is scalability: doubling the cores doesn't double the contention because the network grows with them. NoCs are central to large GPUs, AI accelerators, and chiplet-based designs — when separate dies are bonded together, the NoC extends across the package to stitch them into one coherent system.

A NoC trades latency for scalability: a packet may hop through several routers, so it's slower than a direct wire for two nearby blocks, but it scales to hundreds of endpoints where a shared bus would collapse.

Also called
NoC片上網路on-chip interconnect