chiplet
For decades the instinct was to cram everything onto one big slab of silicon — the monolithic chip. A chiplet flips that instinct: you break the design into several small, single-purpose dies — a cluster of CPU cores here, an I/O block there, a chunk of cache — and then assemble them together inside one package, wired to each other so tightly they behave almost like one chip. Think of it as switching from carving a statue out of a single block of marble to building with LEGO: instead of one risky, enormous part, you snap together a handful of smaller, proven ones.
Why bother? The headline reason is yield. A defect lands somewhere random on every wafer, so the bigger a die is, the more likely a stray flaw ruins the whole thing — and on a leading-edge node a giant die can be ruinously expensive to throw away. Cut that die into four small ones and a single defect spoils only one small piece; you keep the good ones (known-good die) and toss the cheap loser. Chiplets also let you mix-and-match nodes: the compute cores that crave the newest, priciest process can ride a bleeding-edge node, while the I/O and analog blocks — which barely benefit from shrinking — stay on a cheaper, mature node. And because each chiplet is a self-contained, reusable building block, you can drop the same core complex into a laptop part or a 64-core server part without redesigning it from scratch.
The catch is the seam. Two transistors on the same monolithic die talk over a few microns of wire; two chiplets must shove their signals across a package, which costs more energy and a little latency than staying on-chip. So chiplets lean on dense packaging — sitting side by side on a silicon interposer, or stacked — and on fast, standardized die-to-die links so the boundary stays nearly invisible. UCIe is the open standard emerging to let chiplets from different vendors and nodes plug together the way USB once unified peripherals. AMD's Ryzen and EPYC (separate compute and I/O dies), Intel's tiled processors, and Apple's two-die Ultra parts are all chiplet designs already shipping in volume.
MONOLITHIC DIE CHIPLET PACKAGE +-------------------+ +-----------------------------+ | | | [CPU] [CPU] [ I/O ] [cache]| | cores + I/O + | | die die die die | | cache + analog | | =========================== <- die-to-die links | ALL on one node | | ====== interposer ========= | | one defect = lose| +-----------------------------+ | the whole thing | small dies, each maybe a +-------------------+ DIFFERENT process node
One big monolithic die risks the whole part to a single defect and locks every block to one process node; splitting it into chiplets on an interposer raises yield and lets each die use the node that suits it.
Chiplets trade the simplicity of one die for better economics, so the frontier work is making the die-to-die crossing cheap enough — in energy and latency — that the package behaves like a single chip.