multi-Vt design

Multi-Vt design hands the chip a toolbox of transistors with different threshold voltages (Vt) and lets the tool pick the right one for each gate — like a cyclist with a full set of gears. A low-Vt transistor is the high gear: fast, but it leaks a lot of current. A high-Vt transistor is the low gear: slow, but barely leaks. The trick is to use the gas-guzzling fast transistors only on the few paths that are racing against the clock, and the frugal slow ones everywhere else.

Foundries offer the same logic cell (say, a NAND2) in LVT, SVT, and HVT flavours that are layout-identical but differ in implant doping, so swapping them late in the flow is a drop-in change. A power-recovery optimisation step walks every timing path: where there is positive slack to spare, it downgrades fast LVT cells to leak-stingy HVT cells, often cutting total leakage by 2–10× while keeping timing closed. The danger is over-using LVT on non-critical paths and silently burning standby power.