Memory compiler
A software generator that builds a complete, ready-to-use memory block to order — you type in the size you need and out comes the layout, timing models, and everything to drop it straight into a chip. Designing an SRAM by hand is brutally hard: the bitcell is a hand-crafted analog circuit, and you need decoders, sense amps, precharge, redundancy and timing all stitched around it. A memory compiler tiles a verified bitcell array and assembles all that periphery automatically, so a designer asks for, say, 'a 2048 × 64-bit dual-port SRAM' and gets a full instance in minutes.
Out of one compiler comes a family of options: number of words, word width, single- or multi-port, low-power versus high-speed variants, and assist features. Critically it emits not just the GDSII layout but the abstract views the rest of the flow needs — a timing/power model (.lib), a placement abstract (LEF), and verification models — so the block behaves like any other standard cell to place-and-route and static timing tools. Memory compilers are what make it practical for a single SoC to instantiate hundreds of differently-sized memories.
Compiler bitcells are 'pushed' to the most aggressive design rules a foundry allows, so they often define the densest layout on the whole chip — and are characterized across every process corner the foundry guarantees.