Hold violation
A hold violation means the data arrives too early — so fast that the new value races past a flip-flop and corrupts the same flip-flop's capture of the previous value, like a courier so eager they snatch back yesterday's parcel before you've signed for it. The flip-flop needs the data to stay stable for a short window (the hold time) after the clock edge; if a short, fast path lets the next data sweep in too soon, the captured bit is wrong. The killer detail: this happens on the same clock edge, so making the clock slower does nothing — hold is a structural problem, not a frequency problem.
Hold violations get worse in the fast corner — high voltage, low temperature, fast process — exactly opposite to setup, which is why both must be checked at multiple corners. You fix them by deliberately adding delay: inserting buffers or delay cells on the too-fast path, downsizing drivers, or rebalancing clock skew. They are insidious because a hold-broken chip fails silently in the lab even at slow speeds, and unlike setup you cannot test your way out of it by simply turning the clock down.
Insert ~50 ps of delay buffers on the short path to recover positive hold slack.
Hold fixes are usually done as a late, almost mechanical step after placement and CTS — but over-fixing bloats area and power, and badly placed delay buffers can re-create setup problems, so the two checks are forever in tension.