DRAM cell (1T1C)

The leakiest, cheapest, densest way to store a bit: one transistor and one tiny capacitor. The bit is simply whether the capacitor is charged (1) or empty (0); the lone transistor is a gate that connects the capacitor to the bitline only when its wordline is selected. Picture a bucket with a slow drip leak and a tap on top — you store water (charge) to mean '1', but the bucket steadily empties on its own. That single-transistor simplicity is why DRAM packs gigabytes onto one chip, far denser than 6-transistor SRAM.

The catch is that 'D' for dynamic: the charge leaks away in milliseconds, so the whole array must be refreshed — read out and written back — thousands of times per second, or the data evaporates. Reading is also destructive (sensing the charge drains it), so a sense amplifier must restore each cell after every access. To pack the capacitor into a vanishing footprint, manufacturers build it as a deep trench or a tall stacked pillar reaching up between the metal layers.