Bitline

The vertical wire that carries data into and out of a column of memory cells — the highway down which a stored bit travels to the outside world. Every cell in a column shares the same bitline pair (BL and its complement BLB in SRAM), so the bitline is long, crowded with hundreds of cells tapping onto it, and therefore heavily loaded with parasitic capacitance. Think of it as a shared phone line that an entire street is wired into: only one house may speak at a time, and the longer the line, the slower the signal swings.

During a read, the addressed cell tugs the bitline very gently — a tiny voltage difference of perhaps 50–100 mV develops between BL and BLB — which a sense amplifier then snaps into a clean logic level. During a write, the column driver forcibly drags the bitlines to full rail to overwrite the cell. Bitline capacitance dominates both read speed and energy, so memory designers obsess over keeping columns short and pre-charging the lines before each access.