DRAM refresh

The relentless housekeeping that keeps DRAM from forgetting. Because each DRAM cell's charge slowly leaks away, the memory controller must periodically march through every row, read each cell, and immediately rewrite the value back at full strength — like a librarian who must constantly retrace fading pencil notes before they vanish. Miss the deadline (typically the row's data lives about 64 ms at room temperature) and bits silently flip to wrong values.

Refresh isn't free: while a row is being refreshed it can't serve real reads or writes, so refresh steals bandwidth, and at high temperatures (where leakage is worse) the controller must refresh more often, eating even more. As DRAM density climbs, refresh overhead grows, which is why standards add tricks like temperature-compensated refresh and per-bank or fine-grained refresh to interleave the work. In 'self-refresh' mode, the DRAM refreshes itself with the rest of the system asleep — essential for battery-powered standby.