the five-stage pipeline

The textbook pipeline, borrowed from the classic RISC processors, has five stages — a clean assembly line for one instruction. They are usually abbreviated IF, ID, EX, MEM, WB. Think of them as five workbenches in a row, each doing one job and handing the half-built instruction to the next.

Walk one instruction through. IF (instruction fetch): read the instruction from memory at the address in the program counter, and advance the program counter. ID (instruction decode and register read): figure out what the instruction is and read its source operands from the register file. EX (execute): the ALU does the work — add, subtract, compare, or compute a memory address. MEM (memory access): if it is a load, read data memory; if a store, write it; other instructions do nothing here. WB (write-back): write the result into the destination register. A load truly uses all five; an add only really needs four (it does nothing in MEM) but still passes through to keep the line in lockstep.

Five was not magic — it was a sweet spot where each stage does roughly equal work so the clock can tick once per stage. This is a microarchitecture choice, not part of the instruction set: software sees the same instructions whether the chip has five stages or twenty. The five-stage layout matters because the three classic hazards — structural, data, and control — all show up as conflicts between instructions sitting in different stages of exactly this pipeline, and the cures (forwarding, stalls, branch handling) are easiest to learn here first.