the pipeline-depth tradeoff
If chopping work into 5 stages makes the clock faster, why not chop it into 30 and go faster still? This is the seductive logic of deeper pipelines — and the honest answer is that it works only up to a point, after which adding stages makes the chip slower, hotter, and harder to keep busy. The pipeline-depth tradeoff is the balance between a faster clock from more stages and the rising cost those stages impose on every stall and every misprediction.
On the plus side, more stages means each stage does less work, so the slowest stage is shorter and the clock can tick faster — that is the whole appeal, and chasing it (sometimes called superpipelining) is part of why clock rates rose for years. On the minus side, three penalties grow with depth. First, each stage adds a pipeline-register delay, and these fixed overheads become a larger fraction of an ever-shorter cycle, so doubling the stages does not double the clock. Second, a misprediction must flush more stages, so the branch penalty in cycles climbs in lockstep with depth, fattening the effective CPI. Third, deeper pipes burn more power and area on all those extra registers and forwarding paths.
So more stages is not automatically better — there is a sweet spot, and beyond it the rising CPI from longer flushes overwhelms the shrinking cycle time, making net run time worse. History bears this out bluntly: the deeply pipelined Pentium 4 chased extreme clock rates with around twenty stages and was beaten on real work by shorter, cooler pipelines, helping kill the megahertz race. The craft is to make the pipeline just deep enough that the clock gain outpaces the penalty growth, and no deeper. It is the clearest reminder that GHz alone never measures speed — only run time, through the iron law, tells the truth.
Go from 5 to 10 stages: the clock might rise from 2 GHz to 3 GHz (not 4, because register overhead eats the gain), but a misprediction now flushes maybe 7 cycles instead of 3. If branches mispredict often, the fatter CPI can cancel the faster clock, leaving real run time no better — or worse.
Deeper pipes clock faster but flush more per misprediction; past a sweet spot the rising CPI cancels the clock gain, so depth has diminishing — then negative — returns.
The Pentium 4's deep pipeline and the death of Dennard scaling around 2005 together ended the clock-rate race: you cannot just keep adding stages and raising GHz. This is a major reason the industry pivoted to multicore and accelerators instead.