the single-cycle processor

Picture a chef who insists on finishing one entire dish — chop, cook, plate, serve — before even touching the next order. No matter how simple the dish, the kitchen runs on the rhythm of the slowest possible dish. A single-cycle processor works this way: every instruction, simple or complex, is completed start to finish within one clock tick, and the clock must tick slowly enough for the worst instruction to finish.

In a single-cycle design the datapath is laid out so that, within one clock cycle, the signal can flow all the way from reading the program counter, fetching the instruction, reading registers, computing in the ALU, optionally touching data memory, and writing a result back — all before the clock edge that ends the cycle. Because everything happens in one cycle, the design is wonderfully easy to understand and to reason about: you can trace any instruction in a single pass through the diagram. There are no half-finished instructions to keep track of.

The honest catch is performance. The clock period must be long enough for the longest path through the datapath (the critical path), which is usually a load instruction (PC + instruction memory + register read + ALU + data memory + register write). Every instruction, even a trivial add that needs none of that, is stretched to this same worst-case length. That waste is exactly why real designs move on to multi-cycle and then pipelined organizations. The single-cycle CPU is a teaching scaffold, not a competitive chip.