engineering change order (ECO)

Imagine the chip is a finished apartment building. The walls are up, the wiring is run, the inspector is on the way — and you discover one outlet is in the wrong spot. You do not demolish the building. You open one wall, move that one outlet, patch it, and call the inspector back. An engineering change order, or ECO, is that surgical late fix. After your netlist has been placed, the clock distributed, every wire routed, and the parasitics extracted and checked in static timing analysis (STA), a few paths often still miss timing, or a tiny design-rule (DRC) violation shows up. Redoing the whole place-and-route from scratch would scramble everything that already works and burn days. So instead you touch only the offending spot: swap a slow cell for a faster, larger one, drop in a buffer or two, or re-route a handful of nets, and leave the other million-plus cells exactly where they sit.

The trick is to keep the blast radius tiny. To fix a setup (too-slow) path you speed it up — upsize the weak gates or add buffers so a long wire is driven harder; to fix a hold (too-fast) path you deliberately add delay by inserting buffer or delay cells. The tool then does an incremental place-and-route, legalizing just those new or moved cells into the gaps and stitching only the affected nets, after which you re-run incremental STA to confirm the fix closed the violation without opening a new one nearby. Because each pass is small and local, ECOs are how teams converge on a clean design near the finish line, iterating through STA and DRC/LVS until everything is green and the layout is ready for tapeout.

There are two flavors. A timing or DRC ECO, the kind above, changes no logic — it only adjusts drive strength, buffering, or routing. A functional ECO changes what the circuit actually does, usually to patch a logic bug found late. The most prized version is the metal-only (or 'freeze-silicon') ECO: foundries are expensive partly because of mask sets, and the transistor base layers are the costly ones. If you scatter unused 'spare' cells across the floorplan during placement, a late logic fix can often be wired up purely by re-cutting the upper metal layers to hook those spares in — no new base-layer masks, far cheaper and faster than a full respin.