Dennard scaling

For about forty years, chip designers had a quiet gift hiding behind Moore's law. Robert Dennard observed in 1974 that when you shrink a transistor, you can also shrink the voltage and current that run through it by the same factor. The beautiful consequence: even as you pack twice as many transistors into the same area, the power burned per square millimeter stays roughly constant. So each new generation gave you more transistors AND faster switching AND the same power and heat. That was the free lunch. Smaller meant denser, faster, and cooler all at once, which is why clock speeds climbed from megahertz to gigahertz with each node and nobody had to think too hard about the electric bill.

The lunch stopped being free around 2006, and the reason is physics, not engineering laziness. To run a transistor faster you need a healthy gap between its 'on' voltage and its 'off' threshold. But a transistor never fully turns off; even when idle it leaks a trickle of current, and that leakage grows exponentially as you lower the threshold. By the mid-2000s the supply voltage had dropped so close to the threshold that lowering it further made leakage explode, so voltage simply stopped scaling. Power per area, which Dennard's rule had pinned in place, began climbing every generation. That is the power wall.

Once you cannot drain the heat, you cannot keep raising the clock, and indeed single-core clock speeds flattened out around 3 to 4 GHz right where they sit today. The industry's answer was to stop chasing one screaming-fast core and instead spend the extra transistors Moore's law still delivered on MORE cores running at a sane speed; this is exactly why your phone and laptop went multicore. Dennard scaling ending is the hinge moment the rest of the modern roadmap swings on: every later trick, from FinFET and GAA channels to chiplets, backside power, and dark silicon, is fundamentally a way to keep extracting value from density now that density no longer comes with free speed and free power savings.