complementary FET (CFET)

Picture the two transistors at the heart of every CMOS gate as two houses that, until now, have always sat side by side on the same plot of land. One is the n-type device, the other the p-type, and a logic cell like an inverter needs both. They take up room next to each other, and that side-by-side footprint sets a hard floor on how small a standard cell can get. A complementary FET, or CFET, answers that floor by asking a simple question: what if you stacked one house directly on top of the other instead of building them next to each other? Stack the n-type transistor on top of the p-type (or vice versa) in the same footprint and you roughly halve the area each logic cell needs.

This is the next move after the staircase of devices that came before it. The planar transistor gave way to the FinFET around the 22nm generation once a flat channel could no longer hold off leakage; the FinFET in turn handed off to gate-all-around (GAA) nanosheets around 3nm, where the gate wraps the channel on all four sides for tighter control. Each of those steps reshaped a single transistor to keep it switching cleanly as it shrank. CFET is different in kind: it does not reshape the transistor so much as fold the layout into the third dimension, stacking the complementary pair vertically. It is the structural answer to a layout-density limit, the way GAA was the answer to a leakage limit.

The catch is that building two transistors in one vertical column is genuinely hard. You have to grow or bond the top device over the bottom one, wire both into the cell without the layers fighting for space, and keep the heat from the buried lower device from cooking the whole stack. For that reason CFET today lives in research labs and early development, not in shipping products, and it pairs naturally with other frontier tricks like backside power delivery, which moves the power rails beneath the wafer and frees up the crowded front-side metal that a denser stacked cell would otherwise choke on.