backside power delivery (BSPDN)

For decades, a chip stacked everything on one side of the silicon: dozens of metal layers carrying both the signal wires (the logic talking to itself) and the power wires (feeding every transistor its supply voltage). As features shrank, those two jobs started fighting for the same crowded space — and power had a special problem. The wires bringing current down through that tall stack are thin and resistive, so the supply voltage sags a little on the way down. That sag is IR drop, and it gets worse exactly as the interconnect-scaling limit predicts: skinnier wires mean more resistance, less margin, slower and less reliable logic. Backside power delivery answers that limit by giving power its own real estate. You thin the wafer down and build a second metal network on the back of the silicon, dedicated entirely to delivering power, while the front stack is freed up to do nothing but route signals.

Think of an apartment building that originally ran water, electricity, and hallways all through the same set of shafts — everything elbowing for room. Backside power is like moving all the plumbing to a service corridor behind the building. Now the front halls (signals) are wider and easier to lay out, and the plumbing (power) can use big, short, low-resistance pipes that reach each floor from directly behind it instead of snaking down from the roof. Two wins fall out of this. First, IR drop shrinks, because the back-side power rails are thicker and the current reaches each transistor over a much shorter path. Second, routing congestion eases, because freeing the front layers of all those fat power rails leaves more room for the signal wires that place-and-route was struggling to fit. It is one of the techniques entering volume production around the 2nm generation.