3D integration & chiplets

through-silicon via (TSV)

Every rung below this one has fought the same enemy: distance. A signal that has to crawl out of one chip, across a circuit board, and into the next chip pays for every millimeter in delay, power, and lost bandwidth — that is the memory wall in physical form. A through-silicon via is the brute-force answer: instead of routing a connection sideways and out through the package, you drill straight down. A TSV is a narrow vertical tunnel etched clean through a thinned-down piece of silicon and filled with copper, so a chip can talk to the chip directly above or below it through a path only tens of microns long instead of centimeters.

The trick is that silicon is normally the floor you build transistors on, not something you poke holes through. To make TSVs work, the die is ground down until it is shockingly thin — often around 50 microns, thinner than a sheet of paper — then thousands of microscopic shafts are etched through it, lined with insulation so the copper does not short to the substrate, and filled. Stack several such thinned dies and align their TSVs, and you get a single tall block where every layer is wired to its neighbors by thousands of these vertical wires running in parallel. That parallelism is the whole point: many short, fat connections give you enormous bandwidth at low energy per bit.

This is the plumbing underneath 3D stacking and high-bandwidth memory. HBM is literally a stack of DRAM dies bonded on top of each other and threaded with TSVs, then placed beside a GPU or accelerator on an interposer so the two can exchange data over a very wide, very short bus. Without TSVs you would be back to skinny package pins and long board traces — the exact bottleneck that throttles how fast modern AI chips can be fed.

Route sideways (old)        Stack vertically (TSV)
  ___        ___              [ DRAM die ]==o==o==  <- thinned
 | A |======| B |            [ DRAM die ]==o==o==     ~50um
 |___| long  |___|           [ DRAM die ]==o==o==
   board trace (cm)          [ base die  ]==o==o==
                                  ||  ||
                              TSV tunnels (tens of um)
                              filled with copper

Left: two chips wired the long way through the package and board. Right: dies thinned and stacked, with copper-filled TSVs (o==) carrying signals straight down — many short parallel links instead of a few long ones.

TSVs are increasingly paired with hybrid bonding, which fuses copper pads face-to-face with no solder bumps at all, pushing the vertical connections even denser and shorter as 3D stacking moves toward true logic-on-logic chips.

Also called
TSVthrough-silicon vias硅通孔矽穿孔