a SAR ADC
/ S-A-R, or 'sar' /
The successive-approximation (SAR) ADC is the all-rounder, the workhorse you find inside most microcontrollers. It finds the answer the way you would guess a number between 0 and 100 in twenty questions: by halving the range each time. Is it above 50? Yes. Above 75? No. Above 62? And so on, each guess pinning down one more bit, closing in fast on the exact value. This binary-search strategy gets to the answer in just n guesses for n bits — far fewer steps than counting up one by one.
Here is the machinery. A SAR ADC holds an internal DAC, a single comparator, and a register that builds the answer bit by bit, most significant bit first. It first guesses the MSB: sets the DAC to half scale and asks the comparator, 'is the input above this?' If yes, that bit is a 1 and stays; if no, it is a 0 and is cleared. It then tries the next bit at the quarter mark, then the eighth, narrowing the window in half each step. After n comparisons the register holds the final code. A 12-bit conversion takes 12 comparison steps — one clean trip down the bits.
Why this matters: SAR is the sweet spot of resolution, speed, power, and cost. It comfortably reaches 12 to 18 bits at sample rates from kHz up to several MHz, with low power and no latency (each conversion is complete and independent), which is why it dominates general-purpose data acquisition. The honest requirements: the input must be held steady during the whole search, so a sample-and-hold is essential, and the internal DAC and reference must be accurate to the full resolution, since an error in any guess corrupts that bit forever. It is slower than flash and lower-resolution than sigma-delta, but for most jobs it is exactly right.
A 4-bit SAR converting an input that is 11/16 of full scale tries: above 8/16? yes (bit=1). Above 12/16? no (bit=0). Above 10/16? yes (bit=1). Above 11/16? no (bit=0). Result 1010 = 10, the nearest code below 11/16 — found in just 4 steps.
Binary search down the bits: n comparisons for n bits.
A SAR ADC demands a rock-steady input during conversion — if the signal moves mid-search, early high-bit decisions become wrong and cannot be revisited. That is why a sample-and-hold in front is not optional but built into the architecture.