noise margin

Noise margin is the safety cushion between what a digital output promises to deliver and what the next chip's input demands to see. Real wires pick up electrical noise — spikes from switching currents, hum, crosstalk — that rides on top of the signal. Noise margin is how much of that garbage a logic level can tolerate before a HIGH gets mistaken for a LOW or vice versa. It is the digital world's version of building a bridge stronger than the heaviest truck you expect, so a gust does not collapse it.

There are two of them, computed from the four threshold numbers. The HIGH noise margin is the output's guaranteed HIGH minus the input's required HIGH: NMH = VOH(min) - VIH(min). The LOW noise margin is the input's allowed LOW minus the output's guaranteed LOW: NML = VIL(max) - VOL(max). Worked example in 5 V CMOS: the output guarantees VOH = 4.4 V and the input needs only VIH = 3.5 V, so NMH = 0.9 V; the output pulls down to VOL = 0.1 V and the input tolerates up to VIL = 1.5 V, so NML = 1.4 V. Roughly a volt of noise can land on the wire before anything is misread.

This is why CMOS is prized for noisy environments: its thresholds sit near the middle of the supply and its outputs swing rail to rail, giving margins near a third of the supply voltage. Old TTL, by contrast, has a stingy HIGH margin of only about 0.4 V (2.4 V out versus 2.0 V in), so it is far easier to upset. Noise margin shrinks as supply voltages drop — a 1.2 V chip simply has less room — which is one honest reason low-voltage, high-speed digital boards are harder to get right and lean heavily on good grounding and decoupling.