logic levels
Digital circuits only know two states, 1 and 0, but the wires between chips still carry ordinary voltages. Logic levels are the agreed voltage ranges that stand for those two states — like a country agreeing that any banknote above a certain size is a 'large note' and anything below is 'small'. A voltage near the positive supply means HIGH (logic 1); a voltage near ground means LOW (logic 0); and there is a forbidden zone in the middle that should be crossed quickly and never lingered in.
Different logic families draw the lines in different places. Old 5 V TTL calls anything above 2.0 V a valid HIGH and anything below 0.8 V a valid LOW at the receiver, while a transmitter is guaranteed only to put out at least 2.4 V for HIGH and at most 0.4 V for LOW. CMOS running at 5 V is referenced to its supply: it treats above about 3.5 V (70 percent of supply) as HIGH and below about 1.5 V (30 percent) as LOW, and its outputs swing almost the whole way from rail to rail. Modern chips run at 3.3 V, 1.8 V, even 1.2 V, each with its own thresholds. The point is that HIGH is not one universal voltage — it is a band defined by the family and its supply.
This matters the moment you connect two chips. If one part outputs 3.3 V as its HIGH and another needs at least 3.5 V to recognise HIGH, the link is unreliable even though both speak digital. You must check the datasheet's four key numbers — VOH and VOL (what an output guarantees) and VIH and VIL (what an input demands) — and confirm the output's guaranteed HIGH comfortably exceeds the input's required HIGH, with margin to spare. When they do not line up, you need level shifting.
A 5 V CMOS gate guarantees a HIGH output of at least 4.4 V and reads anything above 3.5 V as HIGH, so it has roughly 0.9 V to spare. A 3.3 V part outputting 3.3 V HIGH fails to clear that 3.5 V bar — they do not interoperate without help.
HIGH and LOW are bands, not single voltages — and each family draws them differently.
A floating input (connected to nothing) is not LOW — it drifts and picks up noise, giving random, unreliable behaviour. Unused CMOS inputs must be tied to a defined level, never left open.