a micro-op
/ MY-kroh-op /
A micro-op is a tiny, simple internal operation that a processor actually executes, broken out from the instruction you wrote. Think of a complicated recipe step like 'make a sandwich' being silently expanded by the kitchen into 'get bread, spread butter, add filling, close' — small, uniform actions a line cook can pipeline. Many modern processors do exactly this: the instruction in your program is the recipe step; the micro-ops are the simple actions the hardware really runs.
This matters most for CISC machines like x86, whose instructions can be complex and variable-length. The chip's decoder cracks each such instruction into one or more micro-ops — each as simple and regular as a RISC instruction (a single load, a single add, a single store) — and a fast, RISC-style back end then schedules and executes the micro-op stream, often out of order. A complex 'read memory, add, write memory' instruction might become three micro-ops; a simple instruction might be just one. Even RISC chips sometimes split a few instructions into micro-ops, but the technique is most associated with making CISC fast.
Micro-ops are the concrete reason the RISC-versus-CISC line is blurred: the visible ISA can be complex, but the silicon underneath runs simple RISC-like operations. Crucially, micro-ops are an implementation detail, completely hidden from software — they are not part of the ISA, they vary from chip to chip, and you cannot name them in a program. (Do not confuse them with the historical 'microcode' of microprogrammed control, which is a related but distinct idea: micro-ops are the simple operations the modern out-of-order engine schedules.)
An x86 'push' instruction does two things: decrement the stack pointer and store a value to memory. A decoder typically cracks it into two micro-ops — one subtract and one store — which the back end can then schedule independently of each other.
One CISC instruction becomes several simple micro-ops the RISC-style engine can pipeline.
Micro-ops are invisible to software and not part of the ISA — they differ between chip generations and vendors. A program never targets micro-ops; it targets the architectural instructions, and the chip decides how to break them down.