a superscalar processor
A basic pipeline is like a single checkout lane at a store: customers move through it one after another, smoothly overlapped, but still one person finishes per moment. A superscalar processor opens several checkout lanes at once. Instead of fetching, decoding, and issuing one instruction per cycle, it fetches and starts several instructions every cycle, so more than one instruction can finish in the same clock tick.
Concretely, a 'two-wide' (or 4-wide, 6-wide…) superscalar core fetches a small bundle of instructions each cycle, decodes them in parallel, and routes them to multiple execution units — perhaps two integer ALUs, a load/store unit, and a floating-point unit. If the instructions in the bundle are independent (enough ILP), several execute simultaneously and the processor's instructions-per-cycle (IPC) rises above 1. The hard part is checking, every cycle, which of the candidate instructions actually can go together: the hardware must detect dependences and hazards among them in real time. This dependence-checking and steering logic is the costly heart of a superscalar front end.
An honest caveat: 'width' is a ceiling, not a guarantee. A 4-wide machine can issue up to four instructions per cycle, but only if the code at that moment offers four ready, independent, hazard-free instructions and the right execution units are free. Real programs rarely sustain the peak, so a 4-wide core does not run 4 times faster than a 1-wide one. Modern superscalars are almost always also out-of-order, because reordering is what keeps the lanes fed when the next-in-line instruction is stalled.
A 2-wide core sees the bundle 'add x3=x1+x2; sub x6=x4+x5'. The two are independent, so both issue this cycle: one goes to ALU0, the other to ALU1, and both retire together — IPC of 2 for this cycle.
Several instructions issued and completed per cycle — when enough of them are independent.
Wider is not free or automatic: peak IPC needs the program to supply that much independent work every cycle, which it rarely does. This gap between peak and sustained IPC is one face of the limits of ILP.