executing a load

A load instruction fetches a value from data memory into a register, like 'lw x5, 8(x1)' meaning 'go to the address x1 + 8, grab what's there, and put it in x5'. It is the instruction that uses the MOST of the datapath, so tracing it shows almost every component working together — and explains why a load usually sets the worst-case timing.

Step by step: (1) Fetch the instruction as usual; PC advances to PC + 4. (2) Read base register x1 from the register file, and extract the 12-bit offset (8) from the instruction. (3) The sign-extender widens that offset to full width. (4) A mux selects the sign-extended offset (not a second register) as the ALU's second input, and the ALU adds x1 + 8 to form the memory address — this is called address calculation. (5) Data memory is read at that address with MemRead asserted, returning the stored value. (6) A mux selects the value from memory (not the ALU result) to write back, and with RegWrite asserted that value lands in x5.

Two muxes did real work here that an arithmetic instruction did not need: one chose the immediate over a register for the ALU's input, and one chose the memory output over the ALU output for the write-back. This longer journey — instruction fetch, then ALU, then memory, then register write — is the critical path that pins a single-cycle clock. It also previews the pipeline's five stages: fetch, decode, execute, memory, write-back.