the interrupt descriptor table (IDT) and interrupt vector
/ EYE-dee-tee /
When a trap, exception, or interrupt fires, the CPU has a split-second question: where is the kernel code that handles this particular event? The interrupt descriptor table is the answer - a table, set up by the kernel during boot, that maps each kind of event to the address of the kernel function that should handle it. Think of it as the kernel's emergency phone directory: dial event number N and it routes you straight to the right responder.
Each kind of event is assigned a small number called its interrupt vector. On x86 there are 256 of them (0 through 255): the low ones are reserved for CPU exceptions (vector 0 is divide-by-zero, vector 14 is the page fault, and so on), and higher ones are used for device interrupts and system calls. The IDT is an array of 256 entries indexed by that vector number; each entry (a 'gate descriptor') holds the address of the handler plus permission bits saying which privilege levels may invoke it. When event number N occurs, the CPU automatically reads IDT entry N, switches to privileged mode, and jumps to the handler address stored there - all in hardware, before any kernel C code runs. The kernel tells the CPU where this table lives by loading a register (lidt on x86 points the CPU at the IDT).
Why it matters: the IDT is the literal wiring between hardware events and kernel code, so understanding it demystifies how a page fault 'magically' reaches the page-fault handler or how a device's signal finds its driver. Two honest caveats: the permission bits in each gate are a security feature - they prevent user code from invoking handlers it should not - and the IDT is x86-specific terminology; other architectures have the same idea under different names (ARM uses an exception vector table), so the concept is universal even though 'IDT' is not.
Misusing this table is catastrophic: a corrupt or wrong entry means the CPU jumps to garbage on the next interrupt, which is an immediate, unrecoverable crash - one reason the IDT is set up early and guarded carefully.
page fault occurs -> CPU reads IDT[14] -> jumps to do_page_fault(). Each entry holds handler address + privilege bits. The kernel loads the table's location once at boot via 'lidt'.
The IDT is an array indexed by interrupt vector; the CPU uses it to jump straight to the matching kernel handler, in hardware.
'IDT' and 'interrupt vector' are x86 names; the concept (a table from event number to handler) is universal but called different things elsewhere (ARM exception vectors, etc.). Also, the privilege bits in each gate are a real security boundary, not bookkeeping - they decide whether user code may trigger that entry.