the interrupt vector table
Imagine a hotel front desk with a small board of buttons, one per kind of emergency: fire, medical, security. When a button is pressed, the desk instantly looks up who to call and dials them. An interrupt vector table is exactly that board of phone numbers for the processor: a list of addresses, one per interrupt or exception, telling the CPU which function to jump to the instant that event happens.
When hardware needs attention — a timer ticks, a byte arrives on a serial port, a button is pressed — it raises an interrupt. The processor must stop what it is doing and run the right handler. But how does it know which handler? It uses an index: each interrupt source has a number, and the vector table is an array indexed by that number, where each slot holds the address of the corresponding interrupt service routine. On a Cortex-M chip the vector table sits at the start of flash and is beautifully regular: slot 0 is the initial stack pointer, slot 1 is the reset vector, then come the system exceptions (NMI, HardFault, SysTick, and so on), then one slot per peripheral interrupt (IRQ0, IRQ1, ...). When interrupt number N fires, the hardware reads slot N, loads that address into the program counter, and your handler runs. The table is just an array of function-pointer-sized words placed at a known address; on Cortex-M that address is itself programmable through a register called the VTOR (vector table offset register), which lets a bootloader and an application each have their own table.
It matters because it is the mechanism that turns 'something happened in hardware' into 'this specific function runs', with no polling and almost no delay. The honest caveats: the table must be at the address the hardware expects (placed by the linker script), every used slot must point at a real, correct handler, and a slot you forgot to fill commonly points at a default 'trap forever' handler — so a mysterious hang in an empty infinite loop is often an unhandled interrupt landing on the default vector. Also, the order of entries is fixed by the chip; you cannot rearrange them.
// Cortex-M vector table layout (each slot = one 32-bit address): // [0] initial stack pointer // [1] Reset_Handler // [2] NMI_Handler // [3] HardFault_Handler // ... // [15] SysTick_Handler // [16] external IRQ 0 (e.g. WWDG) // [17] external IRQ 1 ... // When IRQ number N fires, hardware does: PC <- table[16 + N].
An array of handler addresses indexed by interrupt number. The CPU jumps to table[N] when event N fires — no polling needed.
A frequent bug: an interrupt you enabled but did not provide a handler for lands on the default 'infinite loop' vector, so the device just hangs. A mysterious freeze with no crash often means an unhandled vector, not a logic loop.