Assembly & the CPU

the instruction set architecture (ISA)

/ I-S-A /

If you wanted to give orders to a machine that only understands a fixed vocabulary, you would first need the dictionary: every command it accepts, exactly what each does, what its operands look like, and what registers exist. The instruction set architecture, or ISA, is that dictionary. It is the contract between the hardware and any software that runs on it — the complete list of instructions the CPU understands and the state (registers, flags, memory model) they operate on.

An individual instruction is one entry in that dictionary: a single low-level command like 'add these two registers' or 'load this memory value into a register', encoded as a specific pattern of bytes the CPU can decode. The ISA defines the whole vocabulary of such instructions plus the rules: how many registers there are and their names, how addresses are formed, how big a word is, the encoding of each instruction. Crucially, the ISA is a specification — a promise about behaviour — separate from any one chip that implements it. Intel and AMD both build chips that implement the x86-64 ISA, so the same machine code runs on either.

The ISA is the dividing line that makes machine code portable across chips but not across architectures. A program compiled to x86-64 instructions cannot run on an ARM CPU and vice versa, because the two understand entirely different dictionaries — this is why software is shipped 'for x86-64' or 'for ARM'. It is also the level the compiler ultimately targets: choosing an ISA is choosing which instructions the compiler is allowed to emit.

x86-64, ARM/AArch64, and RISC-V are three ISAs; the same C source compiled for each yields three completely different, mutually unrunnable streams of machine code.

An ISA is the hardware-software contract; an instruction is one entry in its vocabulary.

The ISA (the visible contract — instructions, registers, behaviour) is distinct from the microarchitecture (how a particular chip implements it internally, with pipelines and caches). Two chips can share an ISA yet differ wildly in speed and internals.

Also called
ISAinstruction setarchitecture指令集