CISC versus RISC (x86-64 versus ARM)
/ SISK vs RISK /
There are two broad philosophies for designing an instruction set, and they differ like a Swiss-army knife versus a set of simple, single-purpose tools. CISC, complex instruction set computing, favours many rich instructions, some doing several things at once (a single instruction might read from memory, do arithmetic, and write back). RISC, reduced instruction set computing, favours a small set of simple, uniform instructions where, for example, only dedicated load and store instructions touch memory and everything else works register-to-register.
x86-64 (the architecture in most desktops and laptops) is the classic CISC family: instructions vary in length, can be quite elaborate, and an arithmetic instruction may take a memory operand directly. ARM/AArch64 (the architecture in phones, tablets, and increasingly laptops and servers) is the leading RISC family: instructions are a fixed width, the encoding is regular, and it is a load-store design where computation happens only in registers. Neither is simply 'better': CISC can express more per instruction (handy for code density), while RISC's regularity makes instructions easier to decode quickly and pipeline.
For a working programmer the distinction matters mostly because it shapes what the disassembly looks like and why the same C program looks different on each platform — and because software must be built separately for x86-64 and for ARM. The clean CISC-versus-RISC line has also blurred in practice: modern x86-64 chips internally break complex instructions into simple RISC-like micro-operations, so the philosophies meet in the middle even though the external ISA stays CISC.
On x86-64 add rax, [rbx] adds a memory value directly into a register; the equivalent on AArch64 needs two steps — ldr x1, [x0] then add x2, x2, x1.
CISC lets one instruction touch memory and compute; RISC separates the load from the arithmetic.
RISC does not mean 'fewer total instructions in the manual' — modern ARM has a large manual; it means simpler, more uniform instructions (notably load-store). And 'CISC is slow / RISC is fast' is a myth: real performance depends far more on the microarchitecture than on the CISC-or-RISC label.