Timing path

A timing path is the trail a signal travels through a chip from where it is launched to where it is captured — like a relay race leg with a clear starting gun and a finish line. It begins at a startpoint (a flip-flop's clock pin or an input port), winds through some combinational logic, and ends at an endpoint (another flip-flop's data pin or an output port). Static timing analysis chops the entire design into millions of these short legs and checks each one independently.

Every path has a fixed budget: the data must arrive at the endpoint within one clock period (minus a little safety margin). The path delay is the sum of cell delays (how long each gate takes to flip) plus net delays (how long signals crawl down the wires). There are four canonical path groups — register-to-register (the bread and butter), input-to-register, register-to-output, and the rare input-to-output — and timing closure means making sure all of them, in the millions, meet their budget.