Setup violation

A setup violation means the data signal arrives too late — it shows up at a flip-flop's input after the clock edge has already tried to grab it, like a passenger reaching the gate after the plane has pushed back. The flip-flop needs the data to be stable for a small window (the setup time) before the clock edge; if the path is too slow to make that window, the captured value is wrong or metastable. This is the classic max-delay failure, and it's the violation timing engineers fight hardest, because it directly caps how fast the chip's clock can run.

Because it depends on path delay, a setup violation gets worse in the slow corner — low voltage, high temperature, slow process — and you fix it by making the path faster or the clock slower. Real-world cures include upsizing weak gates, restructuring or pipelining the logic, reducing wire load, applying useful skew to borrow time, or, as a last resort, dropping the target frequency. Speed-binning a CPU is essentially shipping the parts whose worst setup paths still close at a higher clock.