Instruction pipeline
Pipelining is the assembly-line trick that makes processors fast. Instead of fully finishing one instruction before starting the next, a CPU splits each instruction into stages — fetch, decode, execute, memory, write-back — and works on five different instructions at once, each at a different stage, exactly like cars moving down a factory line where one station bolts on wheels while the next paints the body.
A single instruction still takes (say) five cycles to traverse the pipe, but because a new one enters every cycle, the processor finishes one instruction per cycle once the pipe is full — a 5× boost in throughput without speeding up any single step. The catch: the line stalls if one stage needs a result the previous instruction hasn't produced yet, or if a branch makes the next instruction unknown. Modern high-performance cores run 15–20 stage pipelines, which is why a single mispredicted branch can cost a dozen wasted cycles.
Deeper pipelines allow higher clock speeds (each stage does less) but make stalls and mispredictions more expensive — the Pentium 4's 31-stage pipeline was a famous cautionary tale of chasing GHz too far.