Computer architecture & accelerators

Instruction-level parallelism (ILP)

ILP is the hidden parallelism inside a single stream of instructions. Even ordinary code contains operations that don't depend on each other — if line 1 adds A+B and line 2 multiplies C×D, there's no reason to do them one after another. A superscalar processor exploits this by having several execution units and issuing two, four, or more independent instructions every cycle, like a kitchen with multiple chefs each cooking a different dish simultaneously.

To find independent work, modern cores do out-of-order execution: they look ahead in a window of dozens of upcoming instructions, run whichever ones have their inputs ready (not necessarily program order), then quietly retire the results in the original order so the program behaves correctly. This is enormously complex — register renaming, reservation stations, reorder buffers — and the payoff diminishes because real code has dependency chains. That diminishing return is exactly why the industry pivoted from ever-wider single cores to putting many cores on a chip.

VLIW (Very Long Instruction Word) is the opposite philosophy: let the compiler, not the hardware, schedule parallel operations into one wide instruction — simpler silicon, but it lives or dies by the compiler. Intel's Itanium tried this and largely failed.

Also called
ILPsuperscalarout-of-order execution超純量亂序執行