Controllability & observability
These are the twin questions behind all of testability. Controllability asks: can I force this internal node to a chosen 0 or 1 from the chip's inputs? Observability asks: if this node goes wrong, can I see the effect at an output? A node deep inside the logic might be like a light switch buried behind twelve nested doors — technically connected to the outside, but in practice almost impossible to flip (poor controllability) or to watch (poor observability).
To test a fault you need both: you must drive the suspect node to the value that exposes the fault, then propagate the result to an observable pin. A node with great controllability but no observability is like a buried switch you can flip but never see the light — you flip it and learn nothing. DFT exists precisely to raise controllability and observability of internal nodes; a scan flip-flop, for instance, makes its output directly observable and its input directly controllable, instantly solving both for that point.
EDA tools compute numeric controllability/observability scores (e.g. SCOAP) to flag the hard-to-test nodes that most need DFT help.