Advanced verification & UVM

code coverage

Code coverage measures how much of the design's source code your tests actually exercised — automatically, with no human writing goals. The simulator instruments the RTL and reports which lines executed, which branches of each if took both the true and false path, which states of each FSM were entered, and which logic toggled from 0→1 and 1→0. It is the answer to a humbling question: 'after a million cycles of testing, is there code in my design that no test ever even touched?' Often, alarmingly, the answer is yes.

Its great virtue is that it's free and objective; its great limitation is that it measures the design as written, not the design as intended. 100% code coverage only proves every line ran — it cannot know that a missing line should have existed, nor that a line ran but in the wrong scenario. That is why code coverage and functional coverage are partners: code coverage finds dead, untested code; functional coverage confirms the meaningful scenarios were hit. You need both to claim a block is thoroughly verified.

Toggle coverage of 100% on a wide bus can be deceptive — every bit toggled, but perhaps never in a value combination that mattered. Coverage is necessary, never sufficient.

Also called
structural coverage結構覆蓋率