Boundary scan (JTAG)

Boundary scan is scan-chain thinking applied to a chip's outer pins so you can test the connections between chips on a circuit board — not the chips' insides, but the solder joints and traces wiring them together. A ring of special cells sits just inside each I/O pin; chained together, they let a tester drive any pin to a chosen value and read any pin's value purely through a tiny 4-or-5-wire control port, with no physical probe touching the board. This solved the crisis of the 1980s when fine-pitch surface-mount and ball-grid-array packages made the old bed-of-nails probing impossible.

Standardized as IEEE 1149.1 and universally called JTAG (after the Joint Test Action Group that created it), it defines a Test Access Port — TCK clock, TMS mode, TDI in, TDO out, optional TRST reset — and a small state machine that shifts instructions and data through the boundary cells. To test a board, you tell chip A to drive a pattern out of a pin and chip B to capture what it received on the connected pin; a mismatch means a broken or shorted trace. JTAG long outgrew testing — it is now the standard backdoor for programming flash, debugging CPUs, and bringing up boards.