finite-state machine (FSM)
Think of a traffic light. At any moment it's in exactly one situation — green, yellow, or red — and it knows precisely what comes next: green gives way to yellow, yellow to red, red back to green. It never sits half-green, and it never jumps straight from green to red. That's the whole idea of a finite-state machine: a piece of logic that is always in exactly one of a small, fixed set of named states, and that moves between them along well-defined transitions when something happens — a button is pressed, a timer expires, a clock ticks.
An FSM is the standard pattern for control logic — the part of a digital circuit that decides what to do next rather than crunching the numbers. You describe it with three things: the set of states, the rules for moving between them (which usually depend on the current state plus the current inputs), and the outputs each state produces. In hardware that memory of "which state am I in" lives in a register of flip-flops, updated once per clock edge, while a block of combinational logic computes the next state and the outputs from the current state and inputs. This split — state-holding sequential elements feeding combinational decision logic — is exactly what makes an FSM a clean, repeatable way to build controllers, protocol handlers, and sequencers.
FSMs come in two classic flavours, and the difference is where the outputs come from. In a Moore machine the outputs depend only on the current state — read the state, you know the outputs — which makes them steady and easy to reason about, but they react one clock later. In a Mealy machine the outputs depend on the current state and the current inputs, so they can respond in the same cycle, often with fewer states, at the cost of outputs that can glitch or change mid-cycle as inputs wiggle. A handy way to remember it: Moore outputs are labelled on the states; Mealy outputs are labelled on the transitions.
// Three-state controller, binary-encoded.
// next-state logic is combinational; the state register is clocked.
localparam IDLE = 2'd0, RUN = 2'd1, DONE = 2'd2;
reg [1:0] state, next;
always @(posedge clk or negedge rst_n) // sequential: hold the state
if (!rst_n) state <= IDLE; // reset to a known state
else state <= next;
always @(*) begin // combinational: choose next
next = state; // default: stay put
case (state)
IDLE: next = start ? RUN : IDLE;
RUN : next = done ? DONE : RUN;
DONE: next = IDLE;
default: next = IDLE; // recover from illegal states
endcase
endA minimal three-state controller — one clocked register holds the state, a combinational block picks the next one. The reset and `default` keep it in a known, valid state.
"Finite" is the load-bearing word: the machine has a countable, fixed number of states, which is exactly what lets you draw it as a bubble-and-arrow diagram and check it exhaustively — every state and transition can be enumerated and reasoned about. Add unbounded memory (a counter that can climb forever, a stack) and you've left FSM territory for a more powerful model of computation.