sequential logic
Think about a combination lock on a gym locker. Spinning to "12" doesn't open it — what happens next depends on what you dialled before. The lock remembers where it is in the sequence. A plain doorbell is the opposite: press it and it rings, let go and it stops, with no memory of whether you rang it a minute ago. Sequential logic is the digital version of that combination lock. Its outputs depend not only on the inputs right now but also on a stored memory of what came before — the circuit's state. Contrast this with combinational logic, whose output is purely a function of its present inputs, like the doorbell.
What lets a sequential circuit "remember" is a piece of state held in flip-flops or registers — tiny one-bit (or many-bit) memories. And here's the part that makes the whole thing tick, literally: that memory updates only on the edge of a clock signal, the shared heartbeat that marches a clock domain forward in lock-step. On each rising (or falling) clock edge, each clocked flip-flop snapshots its input and holds that value steady until the next edge. (A flip-flop with an enable simply keeps its old value when it isn't enabled.) So a sequential circuit doesn't drift continuously; it advances one discrete step at a time, from state to state, on the beat.
In practice you design sequential logic as a loop: the current state plus the current inputs feed a block of combinational logic that computes two things — the outputs, and the next state, which gets latched back into the flip-flops on the next edge. That structure is exactly a finite-state machine, and it's how counters, traffic-light controllers, communication protocols, and processor control units all get built. The flip side is that the clock now sets your speed limit: all the combinational logic between two flip-flops must settle within one clock period, which is the whole reason engineers obsess over the critical path and timing.
// A simple counter: state (count) advances one step on each clock edge. // (count is a 4-bit register, e.g. reg [3:0] count;) always @(posedge clk) if (rst) count <= 4'b0000; // synchronous reset else count <= count + 1;
A 4-bit counter — its output depends on the previous count, updated on each clock edge, the essence of sequential logic.
"Sequential" here refers to advancing through a sequence of states over time, not to instructions running one-after-another in software. A sequential circuit can update millions of flip-flops at once on a single clock edge — it's parallel in hardware, "sequential" only in that it moves through states step by step.