Assertion & cover-property coverage
An assertion that never fails is reassuring — but it might be lying by silence. If the scenario it guards never actually happened during testing, a passing assertion proves nothing. That is why every assertion has a partner: the *cover property*. Where an assertion says 'this must always be true,' a cover property says 'make sure this interesting situation actually OCCURS,' such as 'a write collides with a read on the same address.' Coverage tools tally which cover properties were hit, exposing the silent assertions that were never put to the test.
In simulation, cover properties measure whether your random stimulus is reaching the corner cases your assertions describe — an assertion with 0% cover is a guard dog that never met an intruder. In formal verification the same cover property is even more powerful: the tool tries to *generate* an input sequence that reaches the scenario, and if it proves the scenario is *unreachable*, that often reveals dead logic or an over-constrained environment. Reaching full assertion-and-cover closure — every assertion proven and every meaningful scenario shown reachable — is a key milestone in verification signoff.
A common false sense of security: a testbench reports 'all assertions passed,' but half of them never triggered because the stimulus never created their preconditions. Always check cover-property hits alongside assertion passes — a vacuous pass is worse than no assertion, because it lulls you.