dynamic power

Think of every wire inside a chip as a tiny bucket that must be filled to represent a 1 and emptied to represent a 0. Every time a bit flips, you pour charge in or tip it out, and pouring takes effort. A chip is doing billions of these flips per second across millions of wires. Dynamic power is the energy cost of all that flipping — the power spent because the chip is actively switching, doing work.

The classic formula captures it: dynamic power is roughly proportional to capacitance times voltage squared times frequency (P is about C times V^2 times f). Capacitance C is how much charge each wire holds; voltage V is the height you must fill it to; frequency f is how often per second you flip. Two of these are the famous levers. Voltage enters squared, so lowering voltage a little cuts power a lot — halving V quarters this term. Frequency enters linearly, so a faster clock costs proportionally more power. (A more careful version multiplies in an activity factor, the fraction of wires that actually flip each cycle, since idle wires cost nothing dynamically.)

This formula is the engine behind nearly every power technique. It explains why dynamic voltage and frequency scaling works: drop both V and f when full speed is not needed and power falls steeply, because the V^2 term makes voltage reduction especially powerful. It explains the megahertz trap: cranking up frequency to chase clock-speed headlines burns power that rises with f and, because the highest clocks demand higher voltage, even faster than f. And it is only half the story — as transistors shrank, static (leakage) power stopped being negligible, and the two together set the power budget that ended Dennard scaling.