沒驗證過，就是壞的

module tb;
  logic [3:0] a, b;
  logic [4:0] sum;
  adder dut (.a(a), .b(b), .sum(sum));   // DUT: the design under test

  initial begin
    a = 4'd7; b = 4'd9;                   // drive inputs
    #1;                                   // let combinational logic settle
    if (sum !== a + b)                    // compare against expected
      $error("bad sum: %0d + %0d gave %0d", a, b, sum);
    $finish;
  end
endmodule

class packet;
  rand bit [7:0] addr;
  rand bit [3:0] len;
  constraint legal { addr < 8'd200; len inside {[1:8]}; }  // stay in the legal space
endclass
// call randomize() in a loop -> thousands of valid, varied stimuli

covergroup cg @(posedge clk);
  coverpoint len    { bins all[] = {[1:8]}; }   // did we see every length 1..8?
  coverpoint state;                              // did we visit every FSM state?
endgroup

// after every request, an ack must arrive within 1 to 3 cycles
property req_gets_ack;
  @(posedge clk) req |-> ##[1:3] ack;
endproperty
assert property (req_gets_ack);