Three walls, named honestly
If you have climbed this far up the ladder, you have met the three walls already, scattered across earlier guides. Here we line them up side by side, because together they decide how big a chip can actually get. None of them is about a single clever qubit. They are about what happens when you try to put thousands of qubits on one piece of silicon and run them all at once.
Wall one is the [[wiring-bottleneck|wiring bottleneck]]: every qubit wants its own cables down into the cold, and cables carry heat as well as signal — so space and cooling run out long before a million qubits. Wall two is [[frequency-crowding|frequency crowding]]: many qubit designs are tuned to specific microwave frequencies, and there is only so much room on the dial before two neighbors land too close and start talking over each other. Wall three is [[qubit-yield|yield]]: real fabrication has spread, so not every qubit on a wafer lands on target — and one bad qubit can spoil a whole patch.
the three scaling walls, side by side
wall what it is why it bites at scale
------------ -------------------- ----------------------------
wiring one+ cable per qubit cables = heat; fridge fills up
freq crowding qubits use set tones too many tones -> overlap
yield fab has spread a few off-target qubits per
wafer; one can spoil a patch
none is a 'better single qubit' problem;
all three are 'many qubits on one chip' problems.When crowding meets yield
The reason these walls are so stubborn is that two of them feed each other. Many superconducting qubits are made with a junction whose frequency is *set during fabrication* — you aim for a target, but you land somewhere in a spread around it. Now picture a grid where every qubit must sit far enough in frequency from its neighbors. If fabrication scatters them, some neighbors drift too close, collide, and the pair becomes hard to control. So a yield problem (spread) becomes a crowding problem (collisions), and the bigger the chip, the more pairs there are to go wrong.
why bigger chips collide more (toy illustration)
target frequencies on a small grid; '.' = on target,
'X' = drifted too close to a neighbor (a collision)
4 qubits 16 qubits
. . . . . X
. . . X . .
. . . .
X . . .
same fab spread, but more qubits = more neighbor
pairs = more chances that two land too close.
collisions grow faster than qubit count.There are real handles on this, and they are exactly the chip-design topics from earlier rungs: aim the junction frequencies more precisely so the spread is tighter; trim or tune qubits after fabrication so a near-miss can be nudged onto target; choose layouts and couplers that tolerate more spread; and lean on tunable elements so a fixed collision is no longer fixed. None of these makes the wall vanish — they push it back, qubit by qubit.
What crossing the walls buys: error correction
Suppose you do scale — thousands of well-behaved qubits on a chip. What is it all *for*? The honest answer is that today's machines are in the [[nisq|NISQ]] era: noisy, intermediate-scale, with no error correction underneath. They can run short programs before noise washes the answer out, and they are genuine scientific instruments — but they are not yet the world-changing computers of the headlines.
The prize on the far side of the walls is [[fault-tolerance|fault tolerance]]: weaving many imperfect physical qubits together so that the *group* behaves like one far better qubit — a [[logical-qubit|logical qubit]] — and errors get caught and corrected as the computation runs. This is what would let a quantum computer run long, useful programs reliably. But it comes at a brutal exchange rate. Depending on how noisy the physical qubits are, one logical qubit can cost hundreds to thousands of physical ones, and a useful machine needs many logical qubits. That is the deep reason the qubit counts you hear are so enormous.
the brutal exchange rate (order-of-magnitude only)
1 logical qubit ~= 100s to 1000s of physical qubits
(depends on physical error rate)
a useful program ~= many logical qubits
+ a working error-correction code
so: useful machine ~= (many) x (100s-1000s)
= a LOT of physical qubits
this is why scaling the three walls matters so much:
fault tolerance simply needs a great many good qubits.Hype, reality, and grounded optimism
So where does that leave the timelines? Honestly uncertain. Crossing the three walls *and* paying the error-correction tax is a multi-step climb, and the size of each step is not yet known. It is entirely reasonable to be excited and to admit, in the same breath, that nobody can credibly put a date on a large fault-tolerant machine. Treat any confident year you are quoted — especially one ending in a round number — as marketing until shown otherwise.
It is just as honest to add that no chip platform has won. Superconducting qubits, trapped ions, neutral atoms, spin qubits in silicon, and photonics each trade strengths for weaknesses, and the three walls hit each one differently. That is not a sign of failure — it is a young field keeping several serious bets open at once. A reader who tells you 'this one modality has clearly won' in 2026 has gotten ahead of the evidence.
- When you read a quantum-chip headline, first ask: is this NISQ-era hardware, or a fault-tolerant claim? They are very different stages.
- Ask which qubit count is meant — raw physical qubits, or error-corrected logical qubits? The gap between them is hundreds to thousands to one.
- Ask whether the demo solved a problem people actually care about, or a contrived one chosen to be hard for classical machines.
- Ask whether the result was independently reproduced, and whether classical methods later caught up — both happen often in this field.