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Quantum Meets the Foundry

The big chip foundries are very good at one thing: making millions of identical transistors, wafer after wafer, with stubborn uniformity. Quantum chips badly need that discipline — for spin qubits especially. This is an honest look at what a 300 mm CMOS line could give the field, and the real reasons it is not as simple as walking in the door.

What a foundry is actually good at

Most quantum chips today are still made the way a small kitchen makes a special dish: a few academic or company labs, a handful of wafers at a time, lots of hand-tuning. A commercial foundry is the opposite — an industrial line built over decades to print billions of transistors with almost eerie sameness. The flagship is the 300 mm CMOS line: a thirty-centimetre silicon wafer that flows through hundreds of tightly controlled steps and comes out carrying enormous, repeatable circuits.

Two foundry virtues are exactly what quantum chips are short of. The first is uniformity: a feature drawn on one side of the wafer comes out nearly identical to the same feature on the other side, and on the next wafer, and the wafer after that. The second is scale: the same recipe runs across the whole wafer at once, so making a thousand devices costs little more than making ten. Quantum hardware is held back by the opposite of both — every device comes out a little different, and almost nothing is mass-produced yet.

Why spin qubits look at the line and smile

Of all the qubit modalities, the spin qubit is the one that fits a foundry most naturally — because it is, at heart, a slightly unusual transistor. A spin qubit is a gate-defined quantum dot: a tiny pocket in silicon where a single electron is trapped, and its spin (up or down) stores the quantum information. The pocket is shaped by metal gates sitting just above the silicon — the very same kind of gates a CMOS line already knows how to make, only smaller and cleaner.

Because the building blocks are so close to ordinary silicon transistors, several foundries and labs have already run spin-qubit devices through real 300 mm lines and reported encouraging device-to-device uniformity. That is a genuine milestone: it hints that the field could one day inherit decades of CMOS know-how instead of reinventing it. But hold the enthusiasm at arm's length — these are still small device counts, the qubits still need extreme cold to work, and uniform geometry is not the same as uniform quantum behaviour.

Borrowing the classical playbook: DFM and EDA

Classical chip design earns its reliability from two disciplines worth borrowing wholesale. The first is design for manufacturability, or DFM: you design only what the line can actually build well, inside rules that keep yield high — minimum widths, allowed spacings, shapes the process likes. The second is EDA, the software that lets you lay out, simulate, and check a chip before any metal is touched, catching mistakes on a screen instead of on a wafer.

The catch is that the quantum versions of these rules are still being written. Classical DFM cares whether a transistor switches correctly; quantum DFM has to care about extra, ghostlier things — whether a layout avoids two-level-system defects, keeps materials low-loss, and spaces qubit frequencies so neighbours do not collide. The scorecard below sketches how much of the classical playbook transfers cleanly, and how much needs a quantum rewrite.

WHAT TRANSFERS FROM CLASSICAL IC -> QUANTUM CHIP

  capability          classical    quantum     transfer?
  ------------------   ----------   ---------   ----------
  uniform lithography  mature       needed      MOSTLY YES
  300 mm wafer scale   mature       early       YES (spin)
  layout / routing EDA mature       adapting    PARTLY
  design rule checks   mature       new rules   PARTLY
  low-loss materials   not a goal   essential   NO -- rework
  qubit freq targeting n/a          essential   NO -- new
  cryo behaviour model n/a          essential   NO -- new

  Legend: YES = borrow directly   PARTLY = adapt the tools
          NO  = the quantum line must invent this part
A rough scorecard: lithography and wafer scale transfer well; EDA and design rules adapt; low-loss materials and qubit-frequency targeting must be invented for the quantum line.

So the honest summary is mixed, not triumphant. The mechanical parts of foundry discipline — patterning, alignment, wafer handling, layout tools — transfer with real effort but no miracle. The parts that decide whether a qubit is any good — its loss, its coherence, its exact frequency — are precisely the parts the classical playbook never had to solve, and they are where the quantum line still has to write its own chapters.

The catch: a clean line is not a low-loss line

Here is the deepest tension, stated plainly. A standard CMOS line is optimised for one thing: transistors that switch fast and reliably. Along the way it deposits materials — certain metals, certain oxides, certain liners — that are perfectly fine for switching but quietly lossy for a qubit. A quantum state is fragile in a way a logic level is not; it leaks away into exactly the kinds of imperfect interfaces a normal line is happy to leave behind. Cleanliness in the classical sense does not guarantee the low-loss materials a qubit needs.

There is a second, sharper catch that scale itself drags in: yield. A foundry can make a thousand qubits at once — but if each one lands at a slightly scattered frequency, some neighbours inevitably crowd together and clash. The more you scale, the more collisions you risk. The little illustration below shows the same target frequencies coming out tight on a good line and scattered on a worse one, and how the scatter turns into collisions you cannot use.

FREQUENCY SCATTER -> COLLISIONS (8 qubits in a row)

  target frequencies (GHz):  each q wants its own slot
        q1   q2   q3   q4   q5   q6   q7   q8
       4.8  4.9  5.0  5.1  5.2  5.3  5.4  5.5

  GOOD line (tight spread, +/- 0.02 GHz):
        |    |    |    |    |    |    |    |
       4.8  4.9  5.0  5.1  5.2  5.3  5.4  5.5
       -> all 8 land in clean slots ........ 8/8 usable

  WORSE line (wide spread, +/- 0.08 GHz):
        |   | |       |  |     |        |  |
      4.79 4.93 4.92 5.11 5.16 5.28  5.42 5.46
              ^^^^^^^^^ q2 and q3 overlap = COLLISION
                          q5 too close to q4
       -> 2 qubits unusable ................ 6/8 usable

  Wider scatter -> more collisions -> lower yield.
Same eight target frequencies, two lines. A tight, uniform process keeps every qubit in its slot; a wider spread makes neighbours overlap and collide, so some qubits cannot be used.

Where does this leave us, honestly? Foundries offer the field something it desperately wants — uniformity and scale, with spin qubits first in line to benefit — and the classical disciplines of DFM and EDA give a head start on the software and the rules. But a quantum line is not a CMOS line with a new mask set; it is a CMOS line whose materials, frequency control, and yield criteria all have to be re-thought for fragile quantum states. The work is real, it is early, and it is genuinely promising. That is the whole story, with no part left flattering and no part left out.