Fighting Loss: Surfaces and Airbridges

Where the loss actually lives

When a qubit slowly forgets its state, the energy has to go somewhere. A surprising amount of it leaks into thin, almost invisible layers right at the surfaces and interfaces of the chip: the few-nanometre skin of native oxide on top of the metal, the place where the metal meets the substrate underneath, and the substrate's own exposed face. These layers are full of tiny atomic-scale flaws that soak up microwave energy. Get them under control and a qubit lives longer; ignore them and no amount of clever circuit design will save you.

The chief culprits are two-level-system defects, usually just called TLS. Each one is a single atom or bond that can sit in either of two positions and flip between them. When a defect happens to flip at the qubit's frequency, it acts like a microscopic absorber, swallowing a sliver of the qubit's energy. There are millions of them scattered through those amorphous oxide skins, and together they are one of the biggest limits on how long today's qubits survive.

Cross-section through one edge of a qubit (not to scale):

   air
  -------------------------------  <- native oxide skin (TLS live here)
  | ####  superconducting film  #### |
  ===================================  <- metal/substrate interface (TLS)
  |                                 |
  |            substrate            |
  |        (silicon or sapphire)    |
  |                                 |
  -----------------------------------

  '#' = the good superconductor
  '-' and '=' = the thin lossy layers (where TLS live)

A slice through a qubit's edge. The metal itself is fine; the lossy parts are the thin oxide skin on top and the buried metal/substrate interface.

How much each layer hurts: participation x loss

Not every lossy layer matters equally. What counts is two things multiplied together. First, how lossy the material itself is — captured by its loss tangent, written tan(delta): a small number that says what fraction of energy a material wastes per cycle. Second, how much of the qubit's electric field actually sits inside that layer — its participation ratio, p. A truly awful material does no harm if the field barely touches it; a mildly lossy layer can dominate if the field crowds into it.

Each layer's contribution to loss:

     loss from a layer  =  p  x  tan(delta)

     p          = participation ratio
                  (fraction of the qubit's E-field in that layer)
     tan(delta) = loss tangent (how lossy the material is)

Total loss = sum over all layers, then turn into a quality factor:

     1 / Q_i  =  sum over layers of ( p_layer x tan(delta)_layer )

     Q_i = internal quality factor  (bigger = lower loss = better)

Example (illustrative numbers only):

     layer              p           tan(delta)     p x tan(delta)
     ----------------   ---------   ------------   --------------
     metal oxide skin   0.001       2e-3           2.0e-6
     metal/substrate    0.0005      1e-3           0.5e-6
     bulk substrate     0.9         1e-7           0.9e-7
     ----------------   ---------   ------------   --------------
     sum (1/Q_i)                                   2.6e-6
     so Q_i ~ 1 / 2.6e-6  =  about 380,000

Loss is participation times loss tangent, summed over layers; its inverse is the internal quality factor Q_i. The numbers are illustrative, not measured values.

Two design moves fall straight out of this little formula. You can lower tan(delta) by making the lossy layer cleaner or thinner — that is what surface treatment does. Or you can lower p by reshaping the circuit so the field spreads out and spends less time at the surface — wider gaps and bigger features push the field into the clean bulk substrate, where tan(delta) is tiny. Real chips do both. This per-layer accounting also gives you a dielectric loss budget: a ranked list of which interface to attack first for the most return.

Two practical fixes: clean surfaces, airbridges

The first fix attacks tan(delta) directly. Surface passivation is a family of cleaning and protecting steps: etch away the native oxide that grew the moment the metal met air, then either cap the fresh surface with a deliberate, lower-loss coating or process it so a thick lossy oxide never regrows. The point is not to add anything exotic — it is to stop the chip from quietly poisoning itself with its own oxide, which is where so many TLS make their home.

Strip the native oxide. A gentle chemical or plasma etch removes the few-nanometre oxide skin that hosts most surface TLS.
Protect the fresh surface fast. Before air gets back in, cap it — a controlled passivation layer — so a thick, messy oxide cannot regrow.
Keep it incremental. Change one step at a time, refabricate, and remeasure — so you can tell which step actually moved the needle.

The second fix is mechanical and clever. On a real chip the ground plane gets sliced into islands by the signal lines that cross it, and those islands can drift to slightly different voltages — which both stirs up stray modes and lets a pulse meant for one qubit bleed into its neighbour. An airbridge is a tiny metal arch, free-standing in vacuum, that hops over a signal line to stitch two patches of ground back together. Because it bridges through empty space, it adds almost no new lossy dielectric — and it knocks down crosstalk at the same time.

Airbridge stitching two ground patches over a signal line:

    ground            ___________            ground
   ========         /            \         ========
   ========        /   airbridge   \        ========
   ========       /  (free-standing) \       ========
   ===============                    ===============
          |                                   |
          |   ==== signal line (passes  ====  |
          |        underneath the arch)       |

  The arch reconnects the two ground sides without
  touching the signal line below it -- mostly vacuum,
  so it adds almost no dielectric loss.

An airbridge arches over a signal line to reconnect two patches of ground. It is mostly empty space, so it suppresses crosstalk while adding little loss.

Did it work? Measuring Q_i

None of this means anything until you measure it. The honest scorecard is the internal quality factor, Q_i — a single number for how many oscillation cycles a resonator rings before its own losses damp it out. High Q_i means low loss. The trick is that you usually do not test it on a full qubit at all; you fabricate plain little resonators with the exact same surfaces and steps, cool them down, and read off their Q_i. It is faster, cheaper, and isolates the material question from everything else going on in a qubit.

There is one twist that makes TLS easy to recognise. TLS defects can only absorb so much energy before they saturate, so at very low drive power — the single-photon level a real qubit actually feels — they bite hardest and Q_i sags. Crank the power up and they fill, step out of the way, and Q_i climbs. That power dependence is a fingerprint: if Q_i is much worse at low power than high power, surface TLS are almost certainly your problem, and surface work is where to spend your effort.

Resonator Q_i vs drive power (sketch, arbitrary units):

  Q_i
   |                                  ____ high power:
   |                            _____/      TLS saturated,
   |                       ____/            loss low, Q_i high
   |                 _____/
   |           _____/
   |     _____/  <- TLS unsaturated here: they absorb,
   |____/          Q_i is low at the single-photon level
   +-------------------------------------------> drive power
     (few photons)                  (many photons)

  A strong low-power dip is the TLS fingerprint.
  A good surface fix lifts the whole left-hand side up.

Q_i rising with drive power is the TLS signature. A successful surface fix raises Q_i at the low-power, single-photon end that real qubits care about.