Lithography and Junction Fabrication

From bare wafer to patterned metal

A superconducting quantum chip starts as a clean, flat slice of insulating crystal — usually silicon or sapphire — called the substrate. Almost the entire chip is just thin metal shapes resting on top of it: the capacitor pads, the wiring, the resonators, and the tiny junctions. The first job is to put metal down and then carve it into exactly the right shapes. Get the shapes wrong by a little, and the qubit's frequency lands off target.

Laying the metal down is called thin-film deposition: inside a vacuum chamber, a source metal is heated or sputtered until its atoms drift across and settle on the cold wafer, building up a film often just a hundred nanometres thick. For the big features — pads and wires — a single clean film of a superconductor like niobium or tantalum is what you want, because the quality of that film quietly sets how long the qubit can hold a quantum state.

To carve shapes, you first coat the wafer with a light- or electron-sensitive film called resist, then draw your design into it. For the very fine parts — and especially for the junction — that drawing is done with electron-beam lithography: a focused beam of electrons traces the pattern point by point, like an impossibly fine pen, reaching features just tens of nanometres across. It is slow and serial, but it is precise enough for the smallest things on the chip.

The whole flow, end to end

Step back and the recipe is short: lay down film, draw the pattern, grow the junction in one go, and remove the leftover metal. The clever bit is in the middle, where a single resist mask is used to make a junction without ever breaking vacuum. Here is the flow as a stage diagram.

QUBIT-CHIP PROCESS FLOW (one junction shown)

  [1] DEPOSIT      clean superconducting film on substrate
        |          (niobium / tantalum, ~100 nm)
        v
  [2] PATTERN      e-beam draws junction shape into resist
        |          (suspended bridge left in the resist)
        v
  [3] EVAPORATE    tilt wafer, deposit metal layer A
        |
        v
  [4] OXIDIZE      let in oxygen -> thin oxide grows on A
        |          (this is the junction barrier!)
        v
  [5] EVAPORATE    re-tilt, deposit layer B over the oxide
        |          ( A / oxide / B  =  the junction )
        v
  [6] LIFT-OFF     dissolve resist -> unwanted metal floats away
        |
        v
      finished junction on chip

Steps 3 through 5 are the heart of it, and they use a trick called shadow evaporation, built around a Dolan-bridge junction. The e-beam pattern leaves a tiny free-standing bridge of resist hanging over a gap. With the wafer tilted one way, evaporated metal lands as a first patch on the substrate. Oxygen is then let in for a controlled moment, growing a whisker-thin oxide on that patch. The wafer is tilted the other way, and a second metal patch is laid down — landing slightly shifted because of the bridge's shadow — so it overlaps the first only where the oxide is. Metal, thin oxide, metal: that overlap is the junction.

The last step, lift-off, is the satisfying one. The wafer is soaked in a solvent that dissolves the leftover resist. Everything sitting on top of the resist — all the metal that did not land directly on the substrate or junction — simply floats off and washes away. What remains is the pattern you actually wanted, junction and all.

Why two junctions are never quite the same

Here is the honest part. Every step above has a little wobble. The bridge in the resist comes out a touch wide or narrow, so the overlap area shifts. The oxidation lets in a hair more or less oxygen, so the barrier ends up a fraction of an atom thicker. The film has a slightly rough edge. None of these is a mistake — they are the ordinary spread of a real physical process. But because critical current depends so steeply on overlap area and oxide thickness, those small wobbles translate into a real spread of qubit frequencies across a chip.

1. Aim for a target junction: pick the overlap area and oxidation so the qubit should land at, say, 5.0 gigahertz.
2. Fabricate a whole chip of them at once — every junction goes through the same evaporation and oxidation.
3. Measure them, and find the frequencies scattered in a band around the target rather than sitting exactly on it.
4. On a chip with many qubits, some neighbours drift close enough to collide — the frequency crowding problem from the design chapters.

So fabrication and design are not separate worlds. The spread you can achieve at the bench is exactly what sets how tightly you can pack qubit frequencies, and that feeds straight back into frequency crowding. Tightening the oxidation, smoothing the films, and measuring-and-trimming junctions after the fact are all active, ongoing work. It is genuinely better than it was a decade ago — and still not solved.

A light touch of the quality math

Fabrication does not only set frequencies; it also sets how lossy the chip is — how fast a quantum state leaks away. There is a clean way to think about that without heavy math. Loss lives in the materials: the surfaces, the oxides, the interfaces between film and substrate. Two numbers capture it. One is how much of the qubit's electric field sits inside a given lossy region — its participation. The other is how lossy that material intrinsically is — its loss tangent. Multiply and add up.

MATERIAL LOSS, KEPT LIGHT

  1 / Q_i  =  sum over regions of  ( p_r  x  tan_d_r )

  Q_i     = internal quality factor (bigger = lower loss)
  p_r     = participation: fraction of the field in region r
  tan_d_r = loss tangent: how lossy region r's material is

  Example, two regions:

    region        p_r        tan_d_r       p_r x tan_d_r
    ----------    -------    ----------    -------------
    bulk crystal  0.90       0.000001         0.0000009
    surface oxide 0.001      0.002            0.0000020
                                          ---------------
                              sum 1/Q_i  =  0.0000029
                              so  Q_i    ~  340,000

  Note: the surface oxide holds almost none of the field,
  yet contributes MORE loss than the whole crystal.

The lesson hiding in those numbers is the whole reason fabrication is hard. A material can hold almost none of the field and still be the leading source of loss, simply because it is lossy enough. That is why people fuss endlessly over surfaces, oxides, and how the resist is cleaned away — the bad actors are thin and nearly invisible. A higher internal quality factor Q_i means a longer-lived qubit, and chasing it is largely a materials-and-process fight, not a circuit-drawing one.