The wire that isn't alone
Picture two garden hoses lying side by side in the grass. Squeeze one of them sharply and the other twitches — not because you touched it, but because the ground beneath them shifted. On a modern chip, metal wires lie far closer together than any two hoses, and the 'ground' they share is a thin sliver of insulator just a few nanometers thick. When one wire switches, it does not politely keep its energy to itself. Through the capacitance between the two wires, it *pushes charge* into its neighbor. The neighbor twitches. That twitch can speed up or slow down a signal, and in timing that means a timing path arrives early or late.
In the first five rungs we treated each net as if it lived alone. We extracted its resistance and capacitance, computed a delay, and added that delay to a path. That model is honest only when wires are fat, far apart, and surrounded by air-like spacing — which is exactly how chips looked in the 1990s. As of interconnect scaling into deep-nanometer nodes, wires became tall, thin, and packed shoulder-to-shoulder. The capacitance to the wire *beside* you began to rival the capacitance to the ground *below* you. The lonely-wire model quietly broke.
How a neighbor steals (or donates) picoseconds
The physics is a single capacitor — the coupling capacitance Cc — bridging the aggressor and victim wires. Charge that flows through a capacitor depends on the rate of *voltage difference* across it: i = Cc · d(Vagg − Vvic)/dt. The key is the *relative* direction of the two edges. When the aggressor rises while the victim is also trying to rise, the aggressor's edge helps pull the victim up faster — the victim speeds up. When the aggressor falls while the victim rises, it fights the victim, dragging the edge out — the victim slows down.
AGGRESSOR ───┐ ┌─── (rising)
│ Cc │
├──┤├─────┤
VICTIM ────┘ └───
Same direction (aggressor ↑ , victim ↑):
victim edge PULLED EARLY -> negative delta delay (speed-up)
Opposite direction (aggressor ↓ , victim ↑):
victim edge PUSHED LATE -> positive delta delay (slow-down)
victim quiet (held low), aggressor ↑:
a GLITCH (noise bump) appears on the victim — a functional hazard
___________/\__________ <- bump that can wrongly clock a flopThe magnitude of that stolen or donated time is what we call crosstalk delay (often the *delta delay*). Two ingredients dominate it. First, the size of Cc relative to the victim's total capacitance — a victim with a heavy load barely notices a small coupling cap, but a lightly loaded net is exquisitely sensitive. Second, the slew (edge speed) of the aggressor: a razor-sharp aggressor edge dumps its charge in a tiny instant, hitting the victim hard; a lazy edge spreads the same charge over time and barely registers. This is why a strong, fast driver on the aggressor net is doubly dangerous — fast edges make sharp aggressors.
The data SI needs: parasitic extraction
None of this analysis is possible without knowing the actual geometry of the wires — and crucially, *which* wires run beside *which*. That knowledge comes from parasitic extraction, the step that reads the finished layout and computes the resistance and capacitance of every net. For pure logic-delay timing we needed only the total capacitance of a net (its load). For signal integrity we need much more: the extractor must split that capacitance into ground capacitance and a *separate coupling capacitance to each specific neighbor*. That neighbor-by-neighbor breakdown is the raw fuel of crosstalk analysis.
*** Coupled-RC view of one victim net (simplified SPEF) *** *D_NET victimNet 12.4 ; total cap on victim = 12.4 fF *CAP 1 victimNet:1 3.2 ; cap to GROUND 2 victimNet:2 aggA:5 4.8 ; COUPLING cap to aggressor A 3 victimNet:3 aggB:2 2.1 ; COUPLING cap to aggressor B *RES 1 victimNet:1 victimNet:2 18.0 ; wire resistance segments ... Lonely-wire STA would have seen one number: 12.4 fF. SI-aware STA sees that 6.9 of those 12.4 fF can be DRIVEN by neighbors.
Notice the trade-off the tools make. If you collapsed every coupling cap onto ground (treating neighbors as if always quiet), you would get an optimistic, fast picture — too rosy. If you doubled every coupling cap (the classic 'Miller factor' of 2×, assuming the neighbor always switches the opposite way), you get a pessimistic, slow picture. Early flows used these crude grounded-cap approximations; modern signal-integrity timing keeps the couplings *coupled* and computes the real delta delay per aggressor, per edge, per timing window.
The other SI villain: IR-drop weakens the driver
Crosstalk is about the wire beside you. The second great signal-integrity effect is about the wire *feeding* you — the power grid. Every gate draws its switching current through a long, resistive ladder of metal from the chip's edge to its source. That metal has resistance R, and current I flowing through it produces a voltage drop V = I·R. The gate at the far end of the grid does not see the full supply rail; it sees a sagging, lower voltage. This is IR-drop.
Why does a power-supply problem show up in *timing*? Because a transistor's drive strength falls with supply voltage — drive current scales roughly with the overdrive (V_DD − V_th). Starve a gate of even 5% of its supply and its edges get measurably lazier, its delay measurably longer. Worse, IR-drop is *dynamic*: it is deepest exactly when many gates switch at once — say, a clock edge launching a whole register bank. So the gates most likely to be on a critical timing path are precisely the ones suffering the largest voltage sag, in the worst possible instant.
Ideal supply With IR-drop
V_DD = 0.75 V V_local = 0.71 V (−40 mV sag, ~5%)
drive current ∝ (V_DD − V_th)
V_th ≈ 0.30 V
ideal overdrive = 0.45 V sagged overdrive = 0.41 V
≈ 9% less drive -> edges slower -> cell delay UP a few %
Net effect: STA must DERATE the cells in the IR-drop hot-spot,
adding delay just like the crosstalk delta delay — both eat slack.Why advanced nodes make this dominate
Crosstalk and IR-drop were footnotes in 1995 and headlines today. The reason is geometry. As nodes shrank, designers could not afford to shrink wire *height* as fast as wire *width* — thin, short wires would be far too resistive. So wires became tall and narrow, like a row of dominoes standing on edge. Two such wires present a large facing sidewall to each other, and the gap between them shrank to a handful of nanometers. The result: sidewall (coupling) capacitance grew to dominate the total, while ground capacitance flattened. The fraction of a net's capacitance that a neighbor can drive went from a rounding error to often more than half.
Wire cross-section, then vs. now (not to scale):
OLD node (wide, short) NEW node (tall, narrow)
┌────────┐ ┌────────┐ ┌─┐ ┌─┐ ┌─┐
│ wire A │ │ wire B │ │A│Cc│B│Cc│C│ ← big facing
└────────┘ └────────┘ │ │ │ │ │ │ sidewalls,
═══════════════════════ │ │ │ │ │ │ tiny gaps
Cground >> Ccoupling └─┘ └─┘ └─┘
═══════════════
Ccoupling ≳ Cground
Same shrink that helped density made neighbors LOUDER.Three trends pile on. Resistive wires mean edges are slewy and slow to recover, so a victim disturbed mid-transition stays disturbed longer. Lower supply voltages mean the same millivolt of noise or IR-drop is a larger *fraction* of the rail — a 40 mV sag is a rounding error at 5 V and a crisis at 0.7 V. And denser logic means more aggressors crammed around every victim, more often switching in the same window. Signal integrity stopped being an optional sign-off check and became a first-class constraint that shapes the design.
Fighting back: routing, shielding, and the SI loop
Because crosstalk is born in the layout, most of the cures live in routing. The cheapest defenses are geometric: keep aggressors and victims from running parallel for long stretches, since coupling grows with the length two wires march side by side. Where a long parallel run is unavoidable, the router can add spacing (push the wires apart — coupling falls steeply with distance), or jog one wire to a different track partway. For the most sensitive nets — clocks, analog references, critical signals — engineers spend real area on shielding: routing a grounded (or VDD) wire on each side so the victim couples to a quiet, non-switching neighbor instead of a noisy one.
- Extract the routed layout with a coupling-aware parasitic extraction run, producing per-net coupling capacitances (a coupled SPEF).
- Run signal-integrity timing: for each victim, find aggressors that can switch in its timing window, compute the delta delay, and update arrival times.
- Fold in IR-drop: derate cells in voltage hot-spots so their delay reflects the supply they truly see.
- Identify the nets whose new, SI-aware delay pushed a path into negative slack — the real violators.
- Fix in the layout: add spacing or shields on those nets, upsize a weak victim driver, or weaken/reschedule a too-strong aggressor — then re-extract and repeat.
Step back and the shape of the whole subject appears. Pure logic-delay timing answers the question 'how long would this path take in a clean, lonely-wire world?' Signal-integrity timing answers the harder, truer question: 'how long does it take when the neighbors are shouting and the power rail is sagging?' Everything you learned about corners, derating, and slack still holds — SI just adds a physically-grounded layer of delay that, at advanced nodes, often decides whether the chip closes timing or comes back from the lab broken.