The Drummer Who Sent No Click Track
Imagine a jazz drummer recording a track for a band on the other side of the world. The polite thing to do would be to send a steady click track alongside the drums so everyone plays in time. But the drummer is cheap and the wire is expensive, so they send only the drums. The band's job is to *feel* the tempo from the hits themselves — to lock onto the beat and tap along, even when the drummer rushes or drags. That is exactly the problem a SerDes receiver faces. The transmitter ships a serialized stream of bits down one differential pair, and no separate clock wire comes with it.
In rung 3 you met the eye diagram — that glowing diamond formed when you fold every bit period on top of itself. The eye tells you there is a window of time, the eye opening, where the signal is unambiguously high or low. To recover the data correctly the receiver must do sampling right at the center of that eye, where the voltage margin is widest and the timing margin is most forgiving. Miss the center and you slide toward the edges where the traces cross, the eye is pinched shut, and ones and zeros become a coin toss. The entire art of clock-and-data-recovery is placing one decision instant, every single bit, in the middle of that diamond.
A Loop That Chases the Edges
How do you build a circuit that taps along to a beat it has never heard? You build a feedback loop, and you give it three jobs: *guess* a clock, *measure* how wrong the guess is, and *correct* it — forever. This is a phase-locked loop (PLL) wearing a slightly different hat. At its heart sits a voltage-controlled oscillator (VCO), an oscillator whose frequency you can nudge up or down with a control voltage. The VCO produces the receiver's best guess of the clock. A phase detector compares the edges of the incoming data against the edges of that recovered clock and answers one question: *am I sampling early, or late?*
The detector's verdict — early or late — is filtered into a smooth control voltage by a loop filter and fed to the VCO. If we are sampling early, the loop slows the VCO a touch so its edges drift back toward the data; if late, it speeds up. Round and round, millions of corrections a microsecond, until the recovered clock's edges sit *exactly* a half-bit away from the data edges — which is to say, the sampling instant lands dead center in the eye. When that settles, we say the loop is locked.
data in ──────────►┌──────────────┐
(transitions) │ PHASE │ early / late
┌─────►│ DETECTOR │──────┐
│ └──────────────┘ ▼
│ ┌─────────────┐
│ │ LOOP FILTER │ (charge pump
│ │ (R + C) │ + capacitor)
│ └─────┬───────┘
│ │ control voltage
│ ┌─────▼───────┐
recovered clk └──────────────────────┤ VCO │
(to samplers) feedback └─────────────┘
Lock condition: recovered-clock edge sits 1/2 bit
after each data edge ⇒ sampler fires at eye center.Bang-Bang vs. Linear: Two Ways to Ask 'Early or Late?'
There are two great families of phase detector, and the difference is whether you ask *how much* you are off, or merely *which way*. A linear detector (the classic Hogge) outputs a pulse whose width is proportional to the phase error — a true analog measure of distance from center. It is informative but needs careful analog design. The other family, dominant in modern multi-gigabit links, is the bang-bang (Alexander) detector. It uses three samples per bit — one at the data center and two at the edges — and asks only a binary question: did the clock edge arrive before or after the data edge? Early or late. Nothing in between.
Alexander (bang-bang) sampling, 3 phases per bit:
e0 d e1
│ │ │
────┴────╳────┴────╳────┴──── data with two edges
▲ edge ▲ edge ▲
edge-smp data-smp edge-smp
Decision rule (per transition):
if e0 != d -> clock is LATE (edge sample already flipped)
if d != e1 -> clock is EARLY (flips before next edge)
if no transition -> HOLD (no info this bit)
Output is just +1 / -1 / 0 — a quantized, noisy nudge.Why does a crude one-bit answer win? Because at 56 GBd it is far easier to build a robust comparator that says 'left or right' than an analog circuit that says 'left by 1.8 picoseconds.' The price you pay is dither: even when perfectly centered, a bang-bang loop keeps hunting back and forth by one quantization step, adding a small self-generated jitter called dither jitter. Designers tame it by making each correction step tiny — the digital equivalent of tapping the steering wheel gently rather than yanking it.
Loop Bandwidth: The One Knob That Rules It All
Now the deepest idea in CDR. How *fast* should the loop chase the data? Crank the loop bandwidth high and the recovered clock follows every wiggle of the incoming edges — great when the transmitter's clock genuinely wanders, but terrible because it also faithfully copies high-frequency noise, dragging the sampling point off center. Set the bandwidth low and the loop is calm and rejects fast jitter beautifully — but it is sluggish, and if the source slowly drifts in frequency the loop falls behind and the eye walks out from under the sampler. Loop bandwidth is the single knob that trades tracking against jitter rejection, and there is no free lunch.
The clean way to see this: a CDR is a high-pass filter for jitter. Jitter slower than the loop bandwidth, the loop *tracks* — the clock moves with the data, so that jitter is harmless. Jitter faster than the loop bandwidth, the loop *rejects* — it cannot react in time, so the clock stays put and that jitter eats straight into your timing margin in the eye. Standards like PCIe and the OIF-CEI specs pin this corner down precisely, often setting the CDR bandwidth near 1/1667 of the bit rate (and demanding a defined slope, e.g. 2nd-order, 40 dB/decade), so that a transmitter and a receiver from different vendors agree on exactly which jitter is the link's problem and which is the chip's.
Jitter transfer of a CDR (how much input jitter reaches the clock):
gain │
1.0 ─┤━━━━━━━━━━━━━━━● ← slow jitter: clock TRACKS it
│ ╲ (passes through, harmless)
│ ╲
│ ╲ -40 dB/dec
0.1 ─┤ ╲
│ ╲___ ← fast jitter: clock REJECTS it
│ ╲ (blocked, hits eye margin)
└────────────────┸────────────► jitter frequency
f_loop
(loop bandwidth)
Mirror view — JITTER TOLERANCE (how much input jitter the
link survives): HIGH at low freq (tracked away), drops to a
flat floor at high freq set by the eye opening.Jitter Tolerance, and Tying It Back to BER
Engineers certify a receiver by sweeping a torture test called jitter tolerance: deliberately inject sinusoidal jitter onto the incoming data at one frequency after another, ramp up its amplitude until the link starts making errors, and record the limit. Plot those limits and you get the jitter-tolerance mask the standard demands. The shape is revealing: at low frequencies you can pour in *enormous* jitter — many unit intervals' worth — because the CDR simply tracks it and the clock rides along. As the jitter frequency climbs past the loop bandwidth, tolerance plummets, flattening to a floor set by how much timing room is left in the eye after ISI and equalization have had their say.
- Recover frequency. On power-up the loop has no idea of the bit rate. It first locks the VCO frequency, often by borrowing a clean reference clock and a frequency detector — the *acquisition* phase.
- Acquire phase. Hand control to the phase detector. The loop walks the sampling clock until its edges sit a half-bit from the data edges — the sampler now fires at eye center.
- Track forever. Stay locked while the source drifts (temperature, supply, spread-spectrum clocking). Loop bandwidth decides how aggressively you follow that drift.
- Place the sample. Every bit, the recovered clock strobes the sampler/slicer at the eye center; the chain of decisions is the recovered data.
Here is the payoff that ties the whole link together. The figure of merit for a SerDes is its bit-error rate (BER) — often a brutal 10⁻¹² or better, one slip in a trillion bits. BER is set by how far the sampling instant sits from the noisy, jittery eye edges. A CDR that locks to the true center, with bandwidth tuned to track real drift yet reject high-frequency jitter, keeps the sampler in the fattest part of the eye and drives BER down. A CDR that mis-centers — too little bandwidth (drift walks the eye away) or too much (it copies jitter back in) — shoves the sample toward the eye edge and BER explodes. Equalization opens the eye; CDR makes sure you look through the middle of it. Get both right and a battered, lossy channel still carries a trillion clean bits.
Putting the Loop on Paper
To make 'loop bandwidth' less mystical, here is a behavioral sketch of a digital bang-bang CDR — the kind you would model before committing to silicon. Notice the two paths feeding the phase: a fast proportional term (the immediate nudge) and a slow integral term (the accumulated frequency offset). Their relative weights *are* the loop bandwidth and damping; tuning these two numbers is the single most consequential decision in CDR design.
// Behavioral bang-bang CDR — one sample (data) per bit.
// phase is in fractions of a unit interval (UI); 0.5 == eye center.
float Kp = 1.0/256; // proportional gain -> loop BANDWIDTH
float Ki = 1.0/65536; // integral gain -> tracks frequency drift
float phase = 0.5; // sampling position within the bit
float freq = 0.0; // accumulated frequency offset (the 'memory')
void on_each_bit(int edge_smp, int data_smp, int prev_data) {
if (prev_data == data_smp) return; // no transition: HOLD, no info
// Alexander rule: edge sample vs the two data bits it sits between
int bb = (edge_smp == prev_data) ? +1 // sampling EARLY -> slow down
: -1; // sampling LATE -> speed up
freq += Ki * bb; // integral path (slow, frequency)
phase += Kp * bb + freq; // proportional + integral
if (phase >= 1.0) phase -= 1.0; // wrap within one UI
if (phase < 0.0) phase += 1.0;
// 'phase' now drives the interpolated sampling clock toward eye center.
}
// Bigger Kp -> wider loop bandwidth -> tracks more, rejects less jitter.
// Smaller Kp -> narrower bandwidth -> calm, but slow to chase drift.That handful of lines hides a beautiful truth: the same proportional-integral structure governs a cruise-controlled car, a thermostat, and a PLL locking a radio. A CDR is simply that universal feedback loop, pointed at the edges of a data stream, asked to do one humble thing a hundred billion times a second — find the beat, and sample in the middle of it.