The finish line
Think back over everything the back-end flow has done. You started from a gate-level netlist and a blank rectangle of silicon. You did floorplanning to decide where the big blocks and pins sit, placement to drop every standard cell into a legal row, clock-tree synthesis to fan the clock out evenly, and routing to draw the actual wires on real metal layers. Then you signed off: you ran extraction and static timing analysis until every path met its budget, and you checked power. The whole sequence — place-and-route plus signoff — was building toward one deliverable. This guide is where you hand it over.
"Tapeout" is the name for that handover. It is the point where you stop *changing* the design and start *shipping* it — you freeze the layout, write it out as a file, and send that file to the place that makes the photomasks. The word is a fossil: decades ago the final design data really did leave the building on a reel of magnetic tape that someone literally taped up and carried to the mask shop. The tape is long gone, but the name stuck, and so did the feeling — once it goes, it is gone. You cannot patch silicon the way you patch software.
# Final signoff STA: prove timing on the WORST corner, not a friendly one. set_analysis_mode -on_chip_variation true ; # apply OCV derating margins report_timing -corner slow_ss_125c -delay setup ; # slowest silicon, hot -> setup report_timing -corner fast_ff_m40c -delay hold ; # fastest silicon, cold -> hold # Tapeout gate: worst slack across ALL corners must be >= 0.
The final signoff checklist
Before anyone clicks "write GDSII," the design has to pass a checklist that the whole team agrees on. It is less glamorous than it sounds and more important than almost anything else: tapeout readiness is a *list of green checkmarks*, and a single red one blocks the whole release. The big three are timing, physical correctness, and power — the same three the back-end flow has been chasing all along, now confirmed one last time on the final, fully-routed layout with real parasitics.
- Timing signed off. Timing signoff confirms every path has non-negative slack — setup and hold both pass — on the final routed netlist, across all relevant process corners and with on-chip variation margins applied. No path failures, no negative slack anywhere.
- DRC clean. A design-rule check confirms the layout obeys every geometric rule the foundry demands — minimum wire widths, spacings, enclosure, density. Zero violations.
- LVS clean. Layout-versus-schematic confirms the geometry you drew matches the netlist you intended — same devices, same connectivity. The chip you laid out *is* the chip you designed.
- Power verified. The power-delivery network is checked for IR-drop (every cell gets enough voltage) and for electromigration (no wire carries so much current it will wear out). Power and ground reach everything, safely.
- ECOs closed and re-verified. Any last-minute engineering change order has been routed in *and* the affected checks re-run — because the very fix that closed timing can open a DRC violation.
Notice the trap built into that last line. These checks are not independent — they are coupled, and fixing one can break another. Upsize a cell to close a timing path and you may now violate a spacing rule; reroute to fix that DRC and you have changed the parasitics, so your timing has to be re-proven. The discipline of tapeout is refusing to sign off on a *stale* result. Every green checkmark must be green on the same, final database — the one you are about to ship.
GDSII: the layout you ship
All those checks pass against a database inside your tools. To send the design out, you flatten it into one self-contained file in a format the mask shop can read. For decades that format has been GDSII — a binary stream that stores your entire chip as pure geometry: a stack of layers, and on each layer a pile of polygons with exact coordinates. That is the whole idea. GDSII does not know what a transistor or a clock is. It knows only: *on layer 31, there is a rectangle from here to there; on layer 49, there is this polygon.* It is the chip described the way a stencil-cutter would describe it — shapes on sheets — not the way a logic designer would.
Picture it as a tall stack of transparencies. The bottom sheets hold the tiny transistor shapes; climb upward and you pass the contact layer, then metal 1, metal 2, and so on up through the thick top metals that carry power. Each sheet is one mask layer, and each is just a flat collection of polygons. Stack every sheet in register and you have the complete physical chip — every wire, every via, every cell — frozen as coordinates. A modern design has billions of these polygons, which is why GDSII (and its leaner successor, OASIS) is binary and tightly packed rather than human-readable text.
# Write the signed-off layout out as the shippable deliverable. # (Vendor-neutral pseudo-commands; real tools differ in syntax.) set_db design_freeze true ; # no more edits past this point write_gds top.gds -layer_map tech.map ; # binary geometry: layers + polygons write_lef top.lef ; # abstract for any parent using this block
Tapeout & the mask shop
Your GDSII file goes to the mask shop — the part of the foundry that turns geometry into glass. For each layer in your stack, they make a photomask: a quartz plate carrying that layer's polygons as an opaque chrome pattern, like an extraordinarily precise stencil. A modern process needs dozens of these masks, one (or several) per layer, and together the full set is the *mask set* for your chip. Building a mask set is the single most expensive, most committing thing your file triggers — it is the reason tapeout feels so final.
But the foundry does not print your polygons exactly as drawn. The features are far smaller than the wavelength of light used to print them, so the light bends and the printed shape comes out rounded and distorted. To compensate, the mask shop runs mask data prep: optical proximity correction (OPC) deliberately *warps* your polygons — adding little serifs and jogs, nudging edges — so that after the light blurs them, what actually lands on the wafer matches what you intended. The mask is not a photo of your layout; it is a pre-distorted version engineered to print correctly.
Handoff to fabrication
Here the back-end track ends and the fab takes over. With your mask set made, the foundry begins fabrication: a bare silicon wafer goes in, and one layer at a time, the chip is built upward. The workhorse of that process is photolithography — shining light through each of your masks to print that layer's pattern into a light-sensitive coating, then etching or depositing material where the pattern says. Layer by layer, mask by mask, your stack of polygon sheets becomes a stack of real physical layers in the silicon.
If you want to see what happens next in detail, that is a whole story of its own — and JOVANA has a track for it. The 'How a Chip Is Made' fab track picks up exactly where your GDSII lands: how wafers are grown, how photolithography prints your masks, how doping makes the CMOS transistors your standard cells were built from, and how thousands of copies of your chip are made side-by-side on one wafer. That track is the manufacturing half of the same journey this one finishes.
What comes back: silicon & bring-up
Weeks or months after tapeout, something extraordinary arrives on your bench: *first silicon* — the very first physical chips made from your masks. After living inside simulators and timing reports for so long, you finally get to power up the real thing. This is bring-up: the careful, methodical process of proving the actual chip does what the design promised. You start small — does it take power without shorting? does the clock toggle? does it come out of reset? — and work outward to the full feature set.
Bring-up is where signoff gets its report card. Every margin you carried — every corner you closed timing on, every variation guard-band, every IR-drop you budgeted — was a bet about how real silicon would behave. If the chip boots and hits frequency across temperature and voltage, those bets paid off. If a path is marginal only when the chip is hot, or a block browns out under load, the silicon is telling you something your decks missed. Sometimes the fix is a small ECO and a cheap *metal-only* re-spin; sometimes it is back to the drawing board.
And that closes the loop. You began this back-end track with a clean netlist and an empty floor; you end it holding a working chip that started as your RTL. Every step in between — floorplan, place, clock tree, route, extract, sign off, tape out — existed to carry intent safely from a description into a thing you can hold. That is the whole craft of physical design and signoff: making sure that what comes back in silicon is exactly what you sent out as GDSII.